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TMS470MF06607 bảng dữ liệu(PDF) 27 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  TMS470MF06607 16/32-Bit RISC Flash Microcontroller
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TMS470MF06607 bảng dữ liệu(HTML) 27 Page - Texas Instruments

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TMS470MF06607
www.ti.com
SPNS157C
– JANUARY 2012
Table 3-10. Debug ROM contents for Debug ROM 1 (M3 ROM) (continued)
ADDRESS OFFSET
DESCRIPTION
VALUE
(see Table 3-9 )
0x010
TPIU(1)
0xFFF4_1002
0x014
ETM(1)
0xFFF4_2002
0x018
Debug ROM 2 (CoreSight ROM)
0x1F90_1003
0x01C
End of Table
0x0000_0000
0x020 - 0xEFC
Unused
0x0000_0000
0xF00 - 0xFC8
Reserved
0x0000_0000
0xFCC
MEMTYPE
0x0000_0001
0xFD0
PID4
0x0000_0000
0xFD4
PID5
0x0000_0000
0xFD8
PID6
0x0000_0000
0xFDC
PID7
0x0000_0000
0xFE0
PID0
0x0000_0000
0xFE4
PID1
0x0000_0000
0xFE8
PID2
0x0000_0000
0xFEC
PID3
0x0000_0000
0xFF0
CID0
0x0000_000D
0xFF4
CID1
0x0000_0010
0xFF8
CID2
0x0000_0005
0xFFC
CID3
0x0000_00B1
(1)
Cortex
™-M3 debug ROM always will have entries for optional components TPIU and ETM. Whether or
not these components are present is determined by bit number 0 of the entry value.
Table 3-11. Debug ROM contents for Debug ROM 2 (CoreSight ROM)
ADDRESS OFFSET
DESCRIPTION
VALUE
(see Table 3-9 )
0x000
ETM-M3
0x0000_1003
0x004
HTM
0x0000_2003
0x008
Trace Funnel
0x0000_3003
0x00C
TPIU
0x0000_4003
0x010
End of Table
0x0000_0000
0x014 - 0xEFC
Unused
0x0000_0000
0xF00 - 0xFCC
Reserved
0x0000_0000
0xFD0
PID4
0x0000_0000
0xFD4
PID5
0x0000_0000
0xFD8
PID6
0x0000_0000
0xFDC
PID7
0x0000_0000
0xFE0
PID0
0x0000_0000
0xFE4
PID1
0x0000_0007
0xFE8
PID2
0x0000_0009
0xFEC
PID3
0x0000_0000
0xFF0
CID0
0x0000_000D
0xFF4
CID1
0x0000_0010
0xFF8
CID2
0x0000_0005
0xFFC
CID3
0x0000_00B1
Copyright
© 2012, Texas Instruments Incorporated
Device Configuration
27
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