TMS470MF06607 datasheet(9/65 Pages) TI2

9 / 65 page

RAM (64KB)

SYSTEM Module

Peripherals

PSA

RAM - ECC

RAM - CLR Space

(64KB)

(A)

RAM - SET Space

(64KB)

(A)

0xFFFFFFFF

0xFFF80000

0xFFF7FFFF

0xFF000000

0xFEFFFFFF

0xFE000000

0x0840FFFF

0x08400000

0x0810FFFF

0x08100000

0x0808FFFF

0x08080000

0x0800FFFF

0x08000000

0x0044FFFF

0x0043FFFF

0x00400000

0x0009FFFF

0x0007FFFF

0x00000000

FLASH (512KB - Bank 0)

FLASH - ECC (Bank 1)

FLASH - ECC (Bank 0)

FLASH (128KB - Bank 1)

TMS470MF06607

www.ti.com

SPNS157C

– JANUARY 2012

2.1

Memory Map Summary

2.1.1

Memory Map

Figure 2-1 shows the TMS470MF06607 memory map.

The RAM supports bit access operation which allows set/clear to dedicated bits without disturbing the other bits; for

detailed description see the Architecture Specification.

Figure 2-1. TMS470MF06607 Memory Map

2.1.2

Memory Selects

Memories in the TMS470M devices are located at fixed addresses. Table 2-2 through Table 2-6 detail the

mapping of the memory regions.

Table 2-2. TMS470MF06607-Specific Memory Frame Assignment

MEMORY FRAME NAME

START ADDRESS

ENDING ADDRESS

MEMORY TYPE

ACTUAL MEMORY

nCS0(1)

0x0000 0000

0x0009 FFFF

Flash

640K Bytes

RAM-CLR

0x0810 0000

0x0810 FFFF

Internal RAM

64K Bytes

RAM-SET

0x0808 0000

0x0808 FFFF

Internal RAM

64K Bytes

CSRAM0(1)

0x0800 0000

0x0800 FFFF

Internal RAM

64K Bytes

CSRAM0(1)

0x0840 0000

0x0840 FFFF

Internal RAM-ECC

64K Bytes

(1)

Additional address mirroring could be present resulting in invalid but addressable locations beyond those listed above. The device may

generate an abort when accessing the unimplemented memory regions of peripheral memories. TI recommends the use of the MPU for

protecting access to addresses outside the intended range of use.

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