TMS470MF06607 datasheet(53/65 Pages) TI2

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TMS470MF06607

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SPNS157C

– JANUARY 2012

Table 5-19. SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = input,

SPInSIMO = input, and SPInSOMI = output)(1)(2)(3)(4)

(see Figure 5-19 and Figure 5-20)

NO.

MIN

MAX

UNIT

tc(SPC)S

Cycle time, SPInCLK(5)

tw(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

2(6)

tw(SPCL)S

Pulse duration, SPInCLK low (clock polarity = 1)

tw(SPCL)S

Pulse duration, SPInCLK low (clock polarity = 0)

3(6)

tw(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 1)

Delay time, SPInSOMI data valid after SPInCLK high

trf(SOMI)+15

tv(SPCH-SOMI)S

(clock polarity = 0)

4(6)

Delay time, SPInSOMI data valid after SPInCLK low

trf(SOMI)+15

tv(SPCL-SOMI)S

(clock polarity = 1)

Valid time, SPInCLK high after SPInSOMI data valid

tv(SOMI-SPCH)S

(clock polarity = 0)

5(6)

Valid time, SPInCLK low after SPInSOMI data valid

tv(SOMI-SPCL)S

(clock polarity = 1)

tsu(SIMO-SPCH)S

Setup time, SPInSIMO before SPInCLK high (clock polarity = 0)

6(6)

tsu(SIMO-SPCL)S

Setup time, SPInSIMO before SPInCLK low (clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK high

tv(SPCH-SIMO)S

(clock polarity = 0)

7(6)

Valid time, SPInSIMO data valid after SPInCLK low

tv(SPCL-SIMO)S

(clock polarity = 1)

1.5tc(VCLK)

2.5tc(VCLK)+

td(SPCH-SENAH)S

Delay time, SPIENAn high after last SPICLK high (clock polarity = 0)

tr(ENAn)

1.5tc(VCLK)

2.5tc(VCLK)+

td(SPCL-SENAH)S

Delay time, SPIENAn high after last SPICLK low (clock polarity = 1)

tr(ENAn)

Delay time, SPIENAn low after SPICSn low (if new data has been

tf(ENAn)+6

td(SCSL-SENAL)S

written to the SPI buffer)

Delay time, SOMI valid after SPICSn low (if new data has been

trf(SOMI)+6

td(SCSL-SOMI)S

written to the SPI buffer)

(1)

The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2)

When the SPI is in Slave mode, the following must be true: tc(SPC)S > 2tc(VCLK) and tc(SPC)S ≥ 90 ns.

(3)

For rise and fall timings, see Table 5-13.

(4)

tc(VCLK) = interface clock cycle time = 1 /f(VCLK).

(5)

When the SPI is in Slave mode, the following must be true: tw(SPCL)S > tc(VCLK), tw(SPCL)S ≥ 30 ns, tw(SPCH)S > tc(VCLK) and tw(SPCH)S ≥ 30

ns.

(6)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Peripheral Information and Electrical Specifications

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