TMS470MF06607 datasheet(44/65 Pages) TI2

44 / 65 page

ECLK

TCLK

TDO

TMS

TDI

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

5.2.4.1

ECLK Specification

Table 5-11. Switching Characteristics Over Recommended Operating Conditions for External Clocks(1)(2)

(see Figure 5-9)

NO.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Pulse duration, ECLK

Under all prescale factor combinations

tw(EOL)

0.5tc(ECLK) - tf

low

(X and N)

Pulse duration, ECLK

Under all prescale factor combinations

tw(EOH)

0.5tc(ECLK) - tr

high

(X and N)

(1)

X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the VBUS interface clock divider ratio determined by the CLKCNTL.[19:16] bits in the

SYS module.

(2)

N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the SYS module.

Figure 5-9. ECLK Timing Diagram

5.2.5

JTAG Timing

Table 5-12. JTAG Scan Interface Timing (JTAG Clock specification 10-MHz and 50-pF Load on TDO

Output)

(see Figure 5-10

NO.

MIN

MAX

UNIT

tc(JTAG)

Cycle time, JTAG low and high period

tsu(TDI/TMS - TCKr)

Setup time, TDI, TMS before TCK rise (TCKr)

th(TCKr -TDI/TMS)

Hold time, TDI, TMS after TCKr

th(TCKf -TDO)

Hold time, TDO after TCKf

td(TCKf -TDO)

Delay time, TDO valid after TCK fall (TCKf)

Figure 5-10. JTAG Scan Timings

Peripheral Information and Electrical Specifications

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