TMS470MF06607 datasheet(8/65 Pages) TI2

8 / 65 page

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

Device Overview

The TMS470MF06607 device is a TMS470M Platform Architecture implemented in F035 130-nm TI

technology. Table 2-1 identifies all the characteristics of the TMS470MF06607 device except the SYSTEM

and CPU, which are generic.

Table 2-1. Device Characteristics

DEVICE DESCRIPTION

CHARACTERISTICS

COMMENTS FOR TMS470MF06607

TMS470MF06607

MEMORY

INTERNAL MEMORY

Pipeline/Non-Pipeline

Flash is pipeline-capable

2 Bank 640K-Byte Flash with

ECC

64K-Byte SRAM with ECC

CRC, 1-channel

PERIPHERALS

For the device-specific interrupt priority configurations, see Table 3-4.

For the peripheral address ranges and their peripheral selects, see Table 2-6.

CLOCK

FMzPLL

Frequency-modulated zero-pin PLL has no external loop filter pins.

GENERAL-PURPOSE I/Os

4 I/O

The GIOA port has up to four (4) external pins with external interrupt

capability.

LIN/SCI

2 LIN/SCI

DCAN

2 DCAN

Each with 16/32 mailboxes, respectively.

MibSPI

2 MibSPI

One MibSPI with eight chip select pins, 16 transfer groups, and a 64

word buffer with parity. A second MibSPI with four chip select pins, 1

enable pin, 8 transfer groups, and a 64 word buffer with parity.

HET with XOR Share

18 I/O

The high-resolution (HR) SHARE feature allows even-numbered HR

pins to share the next higher odd-numbered HR pin structures. This

HR sharing is independent of whether or not the odd pin is available

externally. If an odd pin is available externally and shared, then the

odd pin can only be used as a general-purpose I/O. HET RAM with

parity checking capability.

HET RAM

64-Instruction Capacity

MibADC

10-bit, 16-channel

MibADC RAM includes parity support.

64-word FIFO

CORE VOLTAGE

1.5 V

I/O VOLTAGE

3.3 V

PINS

100

Available in 100-pin package.

PACKAGE

PZ (100 pin)

The 100-pin package designator is PZ.

Device Overview

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