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TMS470MF06607 bảng dữ liệu(PDF) 41 Page - Texas Instruments |
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TMS470MF06607 bảng dữ liệu(HTML) 41 Page - Texas Instruments |
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41 / 65 page ![]() guaranteed fail lower threshold guaranteed pass upper threshold guaranteed fail 1.5 5.0 20.0 50.0 f (MHz) TMS470MF06607 www.ti.com SPNS157C – JANUARY 2012 5.2.3 LPO and Clock Detection The LPOCLKDET module consists of a clock monitor (CLKDET) and 2 low-power oscillators (LPO): a low-frequency (LF) and a high-frequency (HF) oscillator. The CLKDET is a supervisor circuit for an externally supplied clock signal. In case the externally supplied clock frequency falls out of a frequency window, the clock detector flags this condition and switches to the HF LPO clock (limp mode). The OSCFAIL flag and clock switch-over remain, regardless of the behavior of the oscillator clock signal. The only way OSCFAIL can be cleared (and OSCIN be again the driving clock) is a power-on reset. Table 5-8. LPO and Clock Detection PARAMETER MIN TYP MAX UNIT Lower threshold 1.5 5.0 MHz invalid frequency Higher threshold 20.0 50.0 MHz limp mode frequency 9.0 12 14.0 MHz (HFosc) LFosc frequency 79 90 110 kHz HFosc frequency 9.0 12 14.0 MHz Figure 5-6. LPO and Clock Detection Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 41 Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 |
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