TMS470MF06607 datasheet(46/65 Pages) TI2

46 / 65 page

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

5.2.8

Flash Timings

Table 5-15. Timing Requirements for Program Flash

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Flash pump stabilization time

From Sleep Mode to

Standby Mode

From Standby Mode to

Active Mode

tacc_delay

µs

Flash bank stabilization time

From Sleep Mode to

1.9

Standby Mode

From Standby Mode to

0.1

Active Mode

tprog(16-bit)

Half-word (16-bit) programming time

37.5

300

µs

512k-byte programming time(1)

78.7

tprog(Total)

640-k-byte programming time(1)

12.5

98.4

terase(sector)

Sector erase time

1.5

Write/erase cycles at TA = -40 to125

°C with

1000(2)

cycles

15-year Data Retention requirement

Nwec

Write/erase cycles at TA = -40 to 125

°C

EEPROM emulation requirement for 16k

25000(2)(3)

cycles

flash sectors in Bank 1

(1)

tprog(Total) programming time includes overhead of state machine, but does not include data transfer time.

(2)

Flash write/erase cycles and data retention specifications are based on a validated implementation of the TI flash API. Non-TI flash API

implementation is not supported. For detailed description see the F035 Flash Validation Procedure (SPNA127).

(3)

Flash write/erase cycle and data retention specifications are based on an assumed distribution of write/erase cycles over the life of the

product including and even distribution over the rated temperature range and time between cycles. The EEPROM emulation bank has

been qualified as outlined in the JEDEC specification JESD22-A117C.

Peripheral Information and Electrical Specifications

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