TMS470MF06607 datasheet(6/65 Pages) TI2

6 / 65 page

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

1.4

Terms and Acronyms

Table 1-1. Terms and Acronyms

Terms and Acronyms

Description

Comments

A2V

AHB to VBUSP Bridge

The A2V bridge provides the memory interface between the

proprietary TI VBUSP and the ARM AHB bus in the TMS470

platform devices.

ADC

Analog To Digital Converter

AHB

Advanced High-performance Bus

Part of the M3 core

BMM

Bus Matrix Master

The BMM provides connectivity between different bus slave

modules to different bus master modules. Accesses from

different master modules are executed in parallel if no resource

conflict occurs or if the master modules are kept in series

through arbitration

CRC

Cyclic Redundancy Check Controller

DAP

Debug Access Port

DAP is an implementation of an ARM Debug Interface.

DCAN

Controller Area Network

DWD

Digital Watchdog

ECC

Error Correction Code

ESM

Error Signaling Module

GIO

General-Purpose Input/Output

HET

High-End Timer

ICEPICK

In Circuit Emulation TAP (Test Access Port)

ICEPick can connect or isolate a module level TAP to or from a

Selection Module

higher level chip TAP. ICEPick was designed with both

emulation and test requirements in mind.

JTAG

Joint Test Access Group

IEEE Committee responsible for Test Access Ports

JTAG-DP

JTAG Debug Port

JTAG-DP contains a debug port state machine (JTAG) that

controls the JTAG-DP operation, including controlling the scan

chain interface that provides the external physical interface to

the JTAG-DP. It is based closely on the JTAG TAP State

Machine, see IEEE Std 1149.1-2001.

LBIST

Logic Built-In Self Test

Test the integrity of M3 CPU

LIN

Local Interconnect Network

M3VIM

Cortex-M3 Vectored Interrupt Manager

MBIST

Memory Built-In Self Test

Test the integrity of SRAM

MibSPI

Multi-Buffered Serial Peripheral Interface

MPU

Protection Unit

NVIC

Nested Vectored Interrupt Controller

Part of the M3 core

OSC

Oscillator

PCR

Peripheral Central Resource

PLL

Phase-Locked Loop

PSA

Parallel Signature Analysis

RTI

Real-Time Interrupt

SCI

Serial Communication Interface

SECDED

Single Error Correction and Double Error

Detection

STC

Self Test Controller

SYS

System Module

VBUS

Virtual Bus

One of the protocols that comprises CBA (Common Bus

Architecture)

VBUSP

Virtual Bus-Pipelined

One of the protocols that comprises CBA (Common Bus

Architecture)

VREG

Voltage Regulator

Features

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