TMS470MF06607 datasheet(47/65 Pages) TI2

47 / 65 page

TMS470MF06607

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SPNS157C

– JANUARY 2012

5.3

SPIn Master Mode Timing Parameters

Table 5-16. SPIn Master Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = output,

SPInSIMO = output, and SPInSOMI = input)(1)(2)(3)

(see Figure 5-13 and Figure 5-14)

NO.

MIN

MAX

UNIT

tc(SPC)M

Cycle time, SPICLK(4)

256tc(VCLK)

Pulse duration, SPICLK high

0.5tc(SPC)M - tr

0.5tc(SPC)M + 5

tw(SPCH)M

(clock polarity = 0)

2(5)

Pulse duration, SPICLK low (clock polarity =

0.5tc(SPC)M - tf

0.5tc(SPC)M + 5

tw(SPCL)M

Pulse duration, SPICLK low (clock polarity =

0.5tc(SPC)M - tf

0.5tc(SPC)M + 5

tw(SPCL)M

3(5)

Pulse duration, SPICLK high

0.5tc(SPC)M - tr

0.5tc(SPC)M + 5

tw(SPCH)M

(clock polarity = 1)

Delay time, SPISIMO data valid before

0.5tc(SPC)M - 15

td(SIMO-SPCL)M

SPICLK low (clock polarity = 0)

4(5)

Delay time, SPISIMO data valid before

0.5tc(SPC)M - 15

td(SIMO-SPCH)M

SPICLK high (clock polarity = 1)

Valid time, SPISIMO data valid

0.5tc(SPC)M - tf(SPC)

tv(SPCL-SIMO)M

(clock polarity = 0)

5(5)

Valid time, SPISIMO data valid

0.5tc(SPC)M - tr(SPC)

tv(SPCH-SIMO)M

(clock polarity = 1)

Setup time, SPISOMI before SPICLK low

tsu(SOMI-SPCL)M

(clock polarity = 0)

6(5)

Setup time, SPISOMI before SPICLK high

tsu(SOMI-SPCH)M

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK

th(SPCL-SOMI)M

low (clock polarity = 0)

7(5)

Hold time, SPISOMI data valid after SPICLK

th(SPCH-SOMI)M

high (clock polarity = 1)

(C2TDELAY+CSHOLD+2)*

(C2TDELAY+CSHOLD+

Setup time CS active until SPICLK high

tc(VCLK) - tf(SPICS) +

2)*tc(VCLK) - tf(SPICS) +

(clock polarity = 0)

tr(SPICLK)-6

tr(SPICLK)+38

8(5)(6)

tC2TDELAY

(C2TDELAY+CSHOLD+2)*

(C2TDELAY+CSHOLD+

Setup time CS active until SPICLK low

tc(VCLK) - tf(SPICS) +

2)*tc(VCLK) - tf(SPICS) +

(clock polarity = 1)

tf(SPICLK)-6

tf(SPICLK)+38

9(5)(6)

0.5*tc(SPC)M +

Hold time SPICLK low until CS inactive

T2CDELAY*tc(VCLK) +

(clock polarity = 0)

tc(VCLK) - tf(SPICLK) +

tr(SPICS)-28

tr(SPICS)+8

tT2CDELAY

0.5*tc(SPC)M +

Hold time SPICLK high until CS inactive

T2CDELAY*tc(VCLK) +

(clock polarity = 1)

tc(VCLK) - tr(SPICLK) +

tr(SPICS)-28

tr(SPICS)+8

10(6)

C2TDELAY * tc(VCLK) -

C2TDELAY *tc(VCLK)

tSPIENA

SPIENAn sample point

tf(SPICS)

(1)

The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is clear.

(2)

tc(VCLK) = interface clock cycle time = 1 / f(VCLK).

(3)

For rise and fall timings, see Table 5-13.

(4)

When the SPI is in Master mode, the following must be true:

•

For PS values from 1 to 255: t

≥ (PS +1)tc(VCLK) ≥ 90 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

•

For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 90 ns.

(5)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6)

C2TDELAY and T2CDELAY are programmed in the SPIDELAY register.

Peripheral Information and Electrical Specifications

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