TMS470MF06607 datasheet(11/65 Pages) TI2

11 / 65 page

TMS470MF06607

www.ti.com

SPNS157C

– JANUARY 2012

Table 2-6. Peripheral Select Map with Address Range

PERIPHERAL

CONNECTING MODULE

BASE ADDRESS

END ADDRESS

SELECTS

MibSPIP2

0xFFF7_F600

0xFFF7_F7FF

PS[2]

MibSPI1

0xFFF7_F400

0xFFF7_F5FF

LIN/SCI1

0xFFF7_E500

0xFFF7_E5FF

PS[6]

LIN/SCI2

0xFFF7_E400

0xFFF7_E4FF

DCAN2

0xFFF7_DE00

0xFFF7_DFFF

PS[8]

DCAN1

0xFFF7_DC00

0xFFF7_DDFF

ADC

0xFFF7_C000

0xFFF7_C1FF

PS[15]

GIO

0xFFF7_BC00

0xFFF7_BCFF

PS[16]

HET

0xFFF7_B800

0xFFF7_B8FF

PS[17]

2.1.3

Flash Memory

When in pipeline mode, the Flash operates with a system clock frequency of up to 80 MHz (versus a

system clock in non-pipeline mode of up to 28 MHz). Flash in pipeline mode is capable of accessing

128-bit words and provides four 32-bit pipelined words to the CPU.

NOTE

1. After a system reset, pipeline mode is disabled [FRDCNTL[2:0] is 000b, see the Flash

chapter in the TMS470M Series Technical Reference Manual (SPNU495). In other

words, the device powers up and comes out of reset in non-pipeline mode.

2. The flash external pump voltage (VCCP) is required for all operations (program,

erase, and read).

2.1.4

Flash Program and Erase

The TMS470MF06607 device flash contains one 512K-byte memory array (or bank) and one 128K-byte

bank for a total of 15 sectors. These 15 sectors are sized as shown in Table 2-7.

The minimum size for an erase operation is one sector. The maximum size for a program operation is one

16-bit word.

Table 2-7. Flash Memory Banks and Sectors

SECTOR

MEMORY ARRAYS (OR

SEGMENT

LOW ADDRESS

HIGH ADDRESS

NO.

BANKS)

16k

0x0000_0000

0x0000_3FFF

BANK 0

(512K Bytes)

16k

0x0000_4000

0x0000_7FFF

32k

0x0000_8000

0x0000_FFFF

64k

0x0001_0000

0x0001_FFFF

64k

0x0002_0000

0x0002_FFFF

64k

0x0003_0000

0x0003_FFFF

64k

0x0004_0000

0x0004_FFFF

64k

0x0005_0000

0x0005_FFFF

64k

0x0006_0000

0x0006_FFFF

64k

0x0007_0000

0x0007_FFFF

Device Overview

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