PM7344 datasheet(202/293 Pages) PMC

202 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

186

Registers 072H, 172H, 272H and 372H: RXCP Interrupt Enable/Status

Bit

Type

Function

Default

Bit 7

R/W

OOCDE

Bit 6

R/W

HCSE

Bit 5

R/W

FIFOE

Bit 4

OOCDI

Bit 3

UHCSI

Bit 2

Reserved

Bit 1

FOVRI

Bit 0

Unused

FOVRI:

The FOVRI bit is set to logic 1 when the receive FIFO has overrun. The

FOVRI bit position is set to logic 0 when this register is read.

Reserved:

This bit provides no useful functional information for S/UNI-MPH applications.

UHCSI:

The UHCSI bit is set to logic 1 when an uncorrectable header check

sequence (HCS) error is detected. The UHCSI bit position is set to logic 0

when this register is read.

OOCDI:

The OOCDI bit is set to logic 1 when an out of cell delineation (OOCD) defect

is detected or removed. The OOCD defect state is contained in the RXCP

Control Register. The OOCDI bit position is set to logic 0 when this register is

read.

FIFOE:

The FIFOE bit enables the generation of an interrupt a receive FIFO overrun,

or a change of cell alignment (COCA) is detected. When a logic 1 is written

to FIFOE, the interrupt generation is enabled.

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