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PM7344 bảng dữ liệu(PDF) 94 Page - PMC-Sierra, Inc

tên linh kiện PM7344
Giải thích chi tiết về linh kiện  SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE
PDF  293 Pages
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nhà sản xuất  PMC [PMC-Sierra, Inc]
Trang chủ  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7344 bảng dữ liệu(HTML) 94 Page - PMC-Sierra, Inc

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PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
78
Registers 004H, 104H, 204H and 304H: Transmit Interface Configuration
Bit
Type
Function
Default
Bit 7
R/W
TOCTA
0
Bit 6
R/W
TOHINV
0
Bit 5
R/W
TDNINV
0
Bit 4
R/W
TDPINV
0
Bit 3
R/W
TUNI
0
Bit 2
R/W
TFALL
0
Bit 1
R/W
TRISE
0
Bit 0
R/W
TRZ
0
These registers enable the Transmit Interface to generate the required digital
output waveform format.
TOCTA:
The TOCTA bit configures the interface to octet-align the transmit cell stream
to the transmission overhead. This bit has no effect when T1, E1 or J2
formats are selected, since octet alignment is specified for these formats.
When the arbitrary format is selected and TOCTA is set to logic 1, the ATM
cell octets are aligned to the arbitrary transmission format overhead
boundaries (as delineated by the TOHI input). The number of TCLKI periods
between transmission format overhead bit positions must be divisible by 8.
When TOCTA is set to logic 0, no octet alignment is performed, and there is
no restriction on the number of TCLKI periods between transmission format
overhead bit positions.
TOHINV:
The TOHINV bit enables the Transmit Interface to internally invert the signal
on the TFPI/TOHI multifunction pin, changing its active polarity. When
TOHINV is set to logic 1, the TFPI/TOHI input is active low. When TOHINV is
set to logic 0, the TFPI/TOHI input is active high.
TDPINV,TDNINV:
The TDPINV and TDNINV bits enable the Transmit Interface to logically invert
the signals output on the TDP/TDD[x] and TDN/TOHO[x] multifunction pins,
respectively. When TDPINV is set to logic 1, the TDP/TDD[x] output is
inverted. When TDPINV is set to logic 0, the TDP/TDD[x] output is not



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