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PM7344 bảng dữ liệu(PDF) 53 Page - PMC-Sierra, Inc |
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PM7344 bảng dữ liệu(HTML) 53 Page - PMC-Sierra, Inc |
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53 / 293 page ![]() PM7344 S/UNI-MPH DATA SHEET PMC-950449 ISSUE 6 MULTI-PHY USER NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 37 Pin Name Type Pin No. Function TCK Input 103 Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. TMS Input 104 Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. TDI Input 102 Test Data Input (TDI). This signal carries test data into the S/UNI-MPH via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. TDO Tristate Output 101 Test Data Output (TDO). This signal carries test data out of the S/UNI-MPH via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress. TRSTB Input 105 Active low Test Reset (TRSTB). This signal provides an asynchronous S/UNI-MPH test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. TRSTB must be asserted during the power up sequence. Note that if not used, TRSTB must be connected to the RSTB input. VDD_AC[2] VDD_AC[1] VDD_AC[0] Power 88 50 18 Pad Ring Power (VDD_AC[2:0]). These pins should be connected to a well decoupled +5 V DC in common with VDD_DC[3:0] VDD_DC[3] VDD_DC[2] VDD_DC[1] VDD_DC[0] Power 116 86 52 20 DC Power (VDD_DC[3:0]). These pins should be connected to a well decoupled +5 V DC in common with VDD_AC[2:0]. VSS_AC[2] VSS_AC[1] VSS_AC[0] Ground 87 51 19 Pad Ring Ground (VSS_AC[2:0]). These pins should be connected to GND in common with VSS_DC[3:0]. |
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