PM7344 datasheet(85/293 Pages) PMC

85 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Registers 000H, 100H, 200H and 300H: Receive Configuration

Bit

Type

Function

Default

Bit 7

R/W

WORDERR

Bit 6

R/W

CNTNFAS

Bit 5

R/W

RXDMAGAT

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

R/W

MODE[1]

Bit 0

R/W

MODE[0]

These registers are used to configure the receive interfaces of the S/UNI-MPH.

WORDERR:

When the E1 format is enabled, the WORDERR bit determines how frame

alignment signal (FAS) errors are reported. When WORDERR is logic 1, one

or more errors in the seven bit FAS word results in a single framing error

count. When WORDERR is logic 0, each error in a FAS word results in a

single framing error count.

CNTNFAS:

When the E1 format is enabled, the CNTNFAS bit determines whether non-

frame alignment signal (NFAS) errors are reported. When the CNTNFAS bit

is a logic 1, a zero in bit 2 of time slot 0 of NFAS frames results in an

increment of the framing error count. If WORDERR is also a logic 1, the

word is defined as the eight bits comprising the FAS pattern and bit 2 of time

slot 0 of the next NFAS frame. When the CNTNFAS bit is a logic 0, only

errors in the FAS affect the framing error count.

RXDMAGAT:

The RXDMAGAT bit selects the gating of the RDLINT[x] output with the

RDLEOM[x] output when the internal HDLC receiver is used with DMA. When

RXDMAGAT is set to logic 1, the RDLINT[x] DMA output is gated with the

RDLEOM output so that RDLINT is forced to logic 0 when RDLEOM is logic

1. When RXDMAGAT is set to logic 0, the RDLINT[x] and RDLEOM[x]

outputs operate independently.

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