PM7344 datasheet(198/293 Pages) PMC

198 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

182

Registers 070H, 170H, 270H and 370H: RXCP Control

Bit

Type

Function

Default

Bit 7

R/W

HCSPASS

Bit 6

R/W

HCSDQDB

Bit 5

R/W

HCSADD

Bit 4

R/W

HCK

Bit 3

R/W

BLOCK

Bit 2

R/W

DSCR

Bit 1

OOCDV

Bit 0

R/W

FIFORST

FIFORST:

The FIFORST bit is used to reset the receive FIFO. When a logic 1 is written

to FIFORST, the FIFO is immediately emptied, and incoming assigned cells

are ignored. When a logic 0 is written to FIFORST, the receive FIFO

operates normally.

OOCDV:

The OOCDV bit indicates the current out of cell delineation defect state.

When an HCS error is detected in seven consecutive cells, OOCDV is set to

logic 1. When six consecutive cells containing no HCS errors are detected,

OOCDV is set to logic 0.

DSCR:

The DSCR bit controls cell payload descrambling using the self-synchronizing

polynomial x43 + 1. When a logic 1 is written to DSCR, payload descrambling

is enabled. When a logic 0 is written to DSCR, payload descrambling is

disabled.

BLOCK:

The BLOCK bit enables idle/unassigned and user-programmable cell

filtering. When a logic 1 is written to BLOCK, idle/unassigned cells or user-

programmed cells corresponding to the pattern specified in the

Idle/Unassigned Cell Pattern and User-programmable Cell Pattern Registers,

and their associated Cell Mask Registers, are blocked. When a logic 0 is

written to BLOCK, only idle/unassigned cells or user-programmed cells

corresponding to the pattern specified in the Idle/Unassigned Cell Pattern and

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