TMPR4925 datasheet(280/590 Pages) TOSHIBA

280 / 590 page

Chapter 10 PCI Controller

10-18

10.3.9.4 Data Transfer Mode

The Transfer Mode field in the PDMAC Configuration register (PDMCFG.XFRMODE) selects

a data transfer mode for a DMA transaction over the G-Bus. Transfer data size and when a transfer

is started differ mode by mode.

Table 10.3.7 shows the available data transfer modes. Mode 00 performs a single-beat transfer;

Mode 01 performs a burst transfer. In either mode, the PDMAC reads data from the source

address, and after the read cycles are complete, writes the data to the destination address. Source

read and destination write cycles do not overlap.

Table 10.3.7 Data Transfer Modes

G-Bus to the PCI bus

PDMCFG.X

FRMODE

Free FIFO Space

Required for

G-Bus Read

Accesses

(DWORDs)

Number of

DWORDs Read

from the G-Bus

Number of

DWORDs required

in FIFO for PCI

Bus Write

Accesses

Number of

DWORDs Written

to the PCI Bus

Overlaps of PCI

Bus and G-Bus

Cycles

None

16 (Burst)

None

PCI Bus to the G-Bus

PDMCFG.X

FRMODE

Free FIFO Space

Required for

G-Bus Write

Accesses

(DWORDs)

Number of

DWORDs Written

to the G-Bus

Number of

DWORDs

Required in FIFO

for PCI Bus Read

Accesses

Number of

DWORDs Read

from the PCI Bus

Overlaps of PCI

Bus and G-Bus

Cycles

None

16 (Burst)

None

*1:

The last DMA transfer consists of less than 16 DWORDs if the data to be transferred is not a

multiple of 16 DWORDs.

Note:

The amount of data transferred varies, depending on the number of DWORDs present in the

FIFO.

10.3.10 Error Detection, Interrupt Reporting

The PCI Controller reports the four following types of interrupts to the Interrupt Controller (IRC).

•

Normal Operation Interrupt

(Interrupt Number: 20, PCIC)

•

PDMAC Interrupt

(Interrupt Number: 19, PDMAC)

•

Power Management Interrupt

(Interrupt Number: 30, PCIPME)

•

Error Detection Interrupt

(Interrupt Number: 29, PCIERR)

When each cause is detected, an interrupt is reported if the corresponding Status bit is set, and the

corresponding Interrupt Enable Bit is set. The following tables list the name of each interrupt cause, the

Status bit, and the Interrupt Enable bit. Please refer to the explanation of each Status bit for more

information regarding each interrupt cause.

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