TMPR4925 datasheet(279/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-17

(5) DMA Transfer Initiation

Setting the address of the DMA Command descriptor that is at the beginning of the Chain

List in the PDMAC Chain Address Register (PDMCA) automatically initiates DMA

transfer.

First, the values stored in each field of the DMA Command Descriptor that is at the

beginning of the Chain List are read to each corresponding PDMAC Register, then DMA

transfer is performed according to the read values.

If a value other than “0” is stored in the PDMAC Chain Address Register (PDMCA), data

transfer of the size stored in the PDMAC Count Register is complete, then the DMA

Command Descriptor value for the memory address specified by the PDMAC Chain Address

When the Chain Address field value reads a descriptor of “0”, the PDMAC Chain Address

Descriptor at which the Chain Address field value is “0” when read) is held.

(6) Termination Report

When DMA data transfer of all descriptor chains terminates normally, the Normal Chain

Complete bit (NCCMP) of the PDMAC Status Register is set. An interrupt is reported if the

Chain Termination Interrupt Enable bit (MCCMPIE) of the PDMAC Control register

(PDMCFG) is set.

Also, the Normal Data Transfer Complete bit (NTCMP) of the DPMAC Status Register is set

each time the DMA data transfer specified by a DMA Command Descriptor terminates

normally. An interrupt is reported if the Normal Data Transfer Complete Interrupt Enable bit

(NTCMPIE) of the PDMAC Control Register (PDMCFG) is set.

If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits of

the PDMAC Status Register and the transfer is aborted. An interrupt is then reported if the

Error Detection Interrupt Enable bit (ERRIE) of the PDMAC Control register is set.

10.3.9.3 Dynamic Chain Operation

It is possible to dynamically add other DMA Command Descriptor Chains to a DMA Command

Descriptor Chain that is currently being processed when executing DMA data transfer. This is

done according to the following procedure.

(1) DMA Command Descriptor Chain Construction

Constructs a DMA Command Descriptor Chain in memory.

(2) Addition of DMA Command Descriptor Chains

Substitutes the address of the command descriptor that is at the beginning of the descriptor

chain to be added into the Descriptor Chain Address field at the end of the DMA Command

Descriptor Chain that is currently performing DMA transfer.

(3) Chain Enable bit checking

Reads the value of the Chain Enable bit (CHNEN) in the PDMAC Control Register

(PDMCFG). If the read value is “0”, then the Chain Address field value of the DMA

Command Descriptor indicated by the address stored in the PDMAC Chain Address Register

(PDMCA) is written to the PDMAC Chain Address Register (PDMCA).

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