TMPR4925 datasheet(278/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-16

(6) Termination Report

When the DMA data transfer terminates normally, the Normal Data Transfer Complete bit

(NTCMP) of the PDMAC Status Register (PDMSTATUS) is set. An interrupt is then reported

if the Normal Data Transfer Complete Interrupt Enable bit (NDCMPIE) of the PDMAC

Control Register is set.

If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits of

the PDMAC Status Register and the transfer is aborted. An interrupt is then reported if the

Error Detection Interrupt Enable bit (ERRIE) of the PDMAC Control register is set.

10.3.9.2 Chain DMA

DMA Command Descriptors are 4 DWORD (16-Byte) data structures indicated in Table 10.3.6

that are placed in memory.

Storing the starting memory address of another DMA Command Descriptor in the Offset 0

Chain Address Field makes it possible to configure a chain list for the DMA command Descriptor.

Set “0” in the Chain Address field of the DMA Command Descriptor at the end of the chain list.

When the DMA transfer specified by one DMA Command Descriptor ends, the PDMAC reads

the next DMA Command Descriptor that the Chain Address field automatically points to, then

continues the DMA transfer. Such continuous DMA transfer that uses multiple descriptors in a

chain format is referred to as the Chain DMA mode.

When a DMA Command Descriptor is placed to an address that does not extend across a 32

DWORD boundary in memory, this transfer method is more efficient since data can be read by a

single G-Bus Burst Read transaction.

Table 10.3.6 DMA Command Descriptors

Offset Address

Field Name

Transfer Destination Register

0x00

Chain Address

PDMAC Chain Address Register (PDMCA)

0x04

G-Bus Address

PDMAC G-Bus Address Register (PDMGA)

0x08

PCI Bus Address

PDMAC PCI Bus Address Register (PDMPA)

0x0c

Count

PDMAC Count Register (PDMCTR)

The DMA transfer procedure is as follows when in the Chain DMA mode.

(1) Count Register Setting

Sets “0” to the PDMAC Count Register (PMDCTR).

(2) DMA Command Descriptor Chain Construction

Constructs the DMA Command Descriptor Chain in memory.

(3) PDMAC Status Register (PDMSTATUS) Clearing

Clears any remaining status from a previous DMA transfer.

(4) PDMAC Control Register (PDMCFG) Setting

Clears the Channel Reset bit (CHRST) and makes settings such as the data transfer direction

(XFRDIRC) and the burst mode (BRSTMD).

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