TMPR4925 datasheet(342/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-80

10.4.52 P2G I/O Space Control Register (P2GIOCTR)

0xD19C

Reserved

: Type

: Initial value

AM[15:8]

Reserved

P2GIOEN

BSWAP

R/W

R/W : Type

0x00

0/1

: Initial value

Bits

Mnemonic

Field Name

Description

31:16



Reserved



15:8

AM[15:8]

Address Mask

PCI-Bus to G-Bus Address Mask (Initial value: 0x00, R/W)

Sets the bits to be subject to address comparison. See 10.3.5 for more information.

When setting a I/O space size of 256 B (0x0000_0100) for example, the value

becomes 0x00.

7:2



Reserved



P2GIOEN

I/O Space Enable

Target I/O Space Enable (Initial value: 0, R/W) Controls whether the I/O Space for

target access is valid or invalid.

When this bit is set to invalid, Writes to the I/O Space Base Address Register of the

PCI Configuration Register become invalid. Also, “0” is returned to Reads as a

response.

1: Validates I/O Space for target access.

0: Invalidates I/O Space for target access.

BSWAP

Byte Swap

Byte Swap Disable

(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W) Sets the byte swapping

of the I/O Space for target access.

0: Do not perform byte swapping.

1: Perform byte swapping.

Please use the default state in most situations. If this bit is changed to “0” when in the

Big Endian Mode, the byte order of transfer to the I/O Space through DWORD (32-bit)

access will not change.

Figure 10.4.52 P2G I/O Space Control Register

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