TMPR4925 datasheet(340/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-78

10.4.50 P2G Memory Space 2 Control Register (P2GM2CTR)

0xD194

Reserved

AM[28:20]

Reserved

R/W

: Type

0x000

: Initial value

Reserved

TPRBL

Reserved

TMCC Reserved MEM1PE P2GM1EN BSWAP

R/W

R/W : Type

010

0/1

: Initial value

Bits

Mnemonic

Field Name

Description

31:29



Reserved



28:20

AM[28:20]

Address Mask

PCI-Bus to G-Bus Address Mask (Initial value: 0x000, R)

Sets the bits to be subject to address comparison. See 10.3.4 for more information.

When setting a memory space size of 256 MB (0x1000_0000) for example, the value

becomes 0x0FFF.

19:11



Reserved



10:8

TPRBL

Target Prefetch

Read Burst

Length

Target Prefetch Read Burst Length (Initial value: 0x3, R/W)

These bits set the G-Bus Burst Size (in DWORDS, (32-bit words)) to be read into the

data FIFO during a target memory Read operation.

0x000: Access and transfer 1DWORD (NO BURST)

0x001: Access and transfer 4 DWORDs of data to the target read FIFO.

0x010: Access and transfer 8 DWORDs of data to the target read FIFO.

0x011: Access and transfer 16 DWORDs of data to the target read FIFO.

0x1xx: Access and transfer 32 DWORDs of data to the target read FIFO.

7:5



Reserved



4TMCC

Target Memory

space 2 Cache

Clear

Target Memory space 1 Cache Clear (Initial value: 0, R/W)

A write of 1 will flush the Target Memory Cache 2. This bit is cleared automatically.

1: Cache Clear

0: Don’t care



Reserved

Note: This bit is always set to “0”. (Initial value: 0, R/W)

MEM2PE

Memory 2

Window Space

Prefetch Enable

Memory 2 Window Prefetch Enable (Initial value: 0, R/W)

If this bit is set, Prefetching of G-Bus data will occur on Target Memory Reads. If this

bit is cleared, 1 Burst of length TPRBL will be done on the G-Bus.

Even if the setting of this bit is changed, prefetchable bits in the Base Address

using the default setting when the PCI Controller is in the Satellite mode.

P2GM1EN

Memory Space 2

Enable

Target Memory Space 2 Enable (Initial value: 0, R/W) Controls whether Memory

Space 2 for target access is valid or invalid.

When this bit is set to invalid, Writes to the Memory Space 2 Lower Base Address

Configuration Register become invalid. Also, “0” is returned to Reads as a response.

1: Validates Memory Space 2 for target access.

0: Invalidates Memory Space 2 for target access.

BSWAP

Byte Swap

Byte Swap Disable

(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W) Sets the byte swapping

of Memory Space 2 for target access.

0: Do not perform byte swapping.

1: Perform byte swapping.

Please use the default state in most situations. If this bit is changed to “0” when in the

Big Endian Mode, the byte order of transfer to Memory Space 2 through DWORD (32-

bit) access will not change.

Figure 10.4.50 P2G Memory Space 2 Control Register

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