S75WS256NDFBAWMB datasheet(106/216 Pages) SPANSION

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104

S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

The following conditions cause the RDY output to be low: during the initial access (in burst mode),

and at the boundary crossing, that occurs every 512 words beginning with address 1FFh.

18.5 Handshaking

The device is equipped with a handshaking feature that allows the host system to simply monitor

the RDY signal from the device to determine when the burst data is ready to be read. The host

system should use the programmable wait state configuration to set the number of wait states

for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of

RDY after OE# goes low.

For optimal burst mode performance, the host system must set the appropriate number of wait

states in the flash device depending on clock frequency. See Set Configuration Register Command

Sequence and Requirements for Synchronous (Burst) Read Operation for more information.

18.6 Writing Commands/Command Sequences

The device has the capability of performing an asynchronous or synchronous write operation.

While the device is configured in Asynchronous read it is able to perform Asynchronous write op-

erations only. CLK is ignored when the device is configured in the Asynchronous mode. When in

the Synchronous read mode configuration, the device is able to perform both Asynchronous and

Synchronous write operations. CLK and AVD# address latch is supported in the Synchronous pro-

gramming mode. During a synchronous write operation, to write a command or command

sequence (which includes programming data to the device and erasing sectors of memory), the

system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the de-

vice, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an

asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when

providing an address, command, and data. Addresses are latched on the last falling edge of WE#

or CE#, while data is latched on the 1st rising edge of WE# or CE# (see ).

The device features an Unlock Bypass mode to facilitate faster programming. Once the device en-

ters the Unlock Bypass mode, only two write cycles are required to program a word, instead of

four.

An erase operation can erase one sector, multiple sectors or the entire device. Table 19.6 indicates

the address space that each sector occupies. A sector address is the address bits required to

uniquely select a sector.

ICC2 in the DC Characteristics section represents the active current specification for the write

mode. The AC Characteristics section contains timing specification tables and timing diagrams for

write operations.

18.7 Accelerated Program/Chip Erase Operations

The device offers accelerated program and accelerated chip erase operations through the ACC

functionACC is intended to allow faster manufacturing throughput at the factory and not to be

used in system operations.

The system can use the Write Buffer Load command sequence. Note that if a Write-to-Buffer-

Abort Reset is required, the full 3-cycle RESET command sequence must be used to reset

the device. Removing VHH from the ACC input, upon completion of the embedded program or

erase operation, returns the device to normal operation. Note that sectors must be unlocked prior

to raising ACC to VHH. When at VIL, ACC locks all sectors. ACC should be at VIH for all other

conditions.

number loaded = the number of locations to program minus 1. For example, if the system will

program 6 address locations, then 05h should be written to the device.)

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