S75WS256NDFBAWMB datasheet(103/216 Pages) SPANSION

103 / 216 page

February 17, 2005 S75WS-N-00_00_A0

S75WS256Nxx Based MCPs

101

Data

Sheet

18 Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated

through the internal command register. The command register itself does not occupy any addres-

sable memory location. The register is composed of latches that store the commands, along with

the address and data information needed to execute the command. The contents of the register

serve as inputs to the internal state machine. The state machine outputs dictate the function of

the device. Table 18.1 lists the device bus operations, the inputs and control levels they require,

and the resulting output. The following subsections describe each of these operations in further

detail.

Table 18.1 Device Bus Operations

Legend: L = Logic 0, H = Logic 1, X = Don’t Care.

18.1

Requirements for Asynchronous Read Operation (Non-Burst)

To read data from the memory array, the system must first assert a valid address on Amax–A0,

while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches

the address. The data will appear on DQ15–DQ0.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The

chip enable access time (tCE) is the delay from the stable CE# to valid data at the outputs. The

output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the

output.

The internal state machine is set for reading array data in asynchronous mode upon device

power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-

tent occurs during the power transition.

Operation

CE#

OE#

WE#

Addresses

DQ15–0

RESET#

CLK

AVD#

Asynchronous Read - Addresses Latched

Addr In

I/O

Asynchronous Read - Addresses Steady State

Addr In

I/O

Asynchronous Write

Addr In

I/O

Synchronous Write

Addr In

I/O

Standby (CE#)

HIGH Z

Hardware Reset

HIGH Z

Burst Read Operations

Load Starting Burst Address

Addr In

Advance Burst to next address with

appropriate Data presented on the Data Bus

Burst

Data Out

Terminate current Burst read cycle

HIGH Z

Terminate current Burst read cycle via RESET#

HIGH Z

Terminate current Burst read cycle and start

new Burst read cycle

Addr In

I/O

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