S75WS256NDFBAWMB datasheet(104/216 Pages) SPANSION

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102

S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

18.2 Requirements for Synchronous (Burst) Read Operation

The device is capable of continuous sequential burst operation and linear burst operation of a pre-

set length. When the device first powers up, it is enabled for asynchronous read operation.

Prior to entering burst mode, the system should determine how many wait states are desired for

the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the

RDY signal will transition with valid data. The system would then write the configuration register

command sequence. See Set Configuration Register Command Sequence for further details.

Table 2-4 shows the address latency scheme for varying frequencies.

Address Latency Scheme for < 84Mhz

The initial word is output tIACC after the rising edge of the first CLK cycle. Subsequent words are

output tBACC after the rising edge of each successive clock cycle, which automatically increments

the internal address counter. Note that the device has a fixed internal address boundary that oc-

curs every 512 words and there is a boundary crossing latency of 4/8 wait states, when

the device is operating at frequencies lower than 56/80Mhz respectively.

During the time the device is outputting data with the starting burst address not divisible by four,

additional waits are required. For example, if the device is operating at frequency of 80Mhz and

if the starting burst address is divisible by four A1:0 = 00, two additional wait state is required.

Table 18.2 Address Latency Scheme for < 56Mhz

Initial

Addr

Cycle

X+1

X+2

X+3

Add ws

X+4

X+5

X+6

0ws

1ws

0ws

1ws

0ws

1ws

0ws

Table 18.3 Address Latency Scheme for < 70Mhz

Initial

Addr

Cycle

X+1

X+2

X+3

Add ws

X+4

X+5

X+6

1ws

Table 18.4 Address Latency Scheme for < 84Mhz

Initial

Addrs

Cycle

X+1

X+2

X+3

Add ws

X+4

X+5

X+6

2ws

1ws

2ws

1ws

2ws

1ws

2ws

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