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CYT4DNJBJS bảng dữ liệu(PDF) 152 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 152 Page - Infineon Technologies AG |
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152 / 209 page  26.10 Clock specifications Table 26-19 Root and intermediate clocks[73, 74] Root Clock Maximumpermitted clock frequency (MHz)[75] Source Maximum permitted clock frequency (MHz)[75] Description PLL/FLL Clock source: ECO/LPECO[76] PLL/FLL Clock source: IMO[77, 78] Integer SSCG Fractional Integer SSCG Fractional CLK_HF0 200 PLL200#0 200 NA NA 191 NA NA Root clock for CPUSS, PERI (CLK_MEM) FLL 100 NA NA 100 NA NA 100 PLL200#0 100 NA NA 95 NA NA PERI (CLK_SLOW, CLK_PERI) FLL 100 NA NA 97 NA NA CLK_HF1 320 PLL400#0 320 313 316 306 300 303 CM7 CPU Core#0, CM7 CPU Core#1 clock FLL 100 NA NA 100 NA NA CLK_HF2 100 PLL200#1 100 NA NA 95 NA NA Peripheral clock root other than CLK_PERI FLL 100 NA NA 97 NA NA CLK_HF3 100 PLL200#0 100 NA NA 95 NA NA Event generator (CLK_REF), clock output on EXT_CLK pins (when used as output) FLL 100 NA NA 97 NA NA CLK_HF4 50 PLL200#0 50 NA NA 47 NA NA ETH Channel#0. Internal clock 50 MHz for RMII, External PHY provides 25 MHz for MII FLL 50 NA NA 48 NA NA CLK_HF5 200 PLL400#1 / PLL400#2 / EXT_CLK 200 196 198 191 187 189 Sound Subsystem #0 root clock, ETH0 TSU clock (CLK_IF_SRSS0) FLL 100 NA NA 100 NA NA CLK_HF6 200 PLL400#1 / PLL400#2 / EXT_CLK 200 196 198 191 187 189 Sound Subsystem #1 root clock (CLK_IF_SRSS1) FLL 100 NA NA 100 NA NA CLK_HF7 200 PLL400#1 / PLL400#2 / EXT_CLK 200 196 198 191 187 189 Sound Subsystem #2 root clock (CLK_IF_SRSS2) FLL 100 NA NA 100 NA NA CLK_HF8 370 PLL400#1 333 326 329 318 312 315 SMIF#0 root clock PLL400#2 333 362 366 318 312 315 FLL NA NA NA NA NA NA Notes 73.Intermediate clocks that are not listed have the same limitations as that of their parent clock. 74.Table indicates guaranteed mapping between a root clock (CLK_HFx) and the PLL. 75.Maximum clock frequency after the corresponding clock source (PLL/FLL + dividers). All internal tolerances and affects are covered by these frequencies. 76.For ECO, LPECO: up to ±150ppm uncertainty of the external clock source are tolerated by design. 77.The IMO operation frequency tolerance is included. 78.ROM and flash boot execution with IMO/FLL at 100 MHz is guaranteed by design. |
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