CYT4DNJBJS datasheet(142/209 Pages) INFINEON

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Datasheet

142

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

26.9

System resources

Table 26-15

System resources

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/

conditions

Power-on reset specifications

SID270

VPOR_R

POR rising trip voltage

1.5

–

2.35

Guaranteed by

design

SID276

VPOR_F

POR falling trip voltage

1.45

–

2.1

SID271

VPOR_H

Level detection hysteresis

–

300

SID272

tDLY_POR

Delay between VDDD rising through

2.3 V and POR reset output rising

through VDDD / 2

––

3µs

Guaranteed by

design

SID273

tPOFF

Power off time

350

–

µs

VDDD < 1.45 V

Does not apply to

SID274A and

SID274B

SID274A POR_RR1

VDDD power ramp rate with robust

BOD - XRES_L asserted

(BOD operation is guaranteed)

––

100

mV/µs Applies to ramp up

and ramp down

SID274B POR_RR1

VDDD power ramp rate with robust

BOD - XRES_L de-asserted

(BOD operation is guaranteed)

1–

100

mV/µs Applies to ramp up

and ramp down

SID275

POR_RR2

VDDD power ramp rate without robust

BOD

100

–

1000

mV/µs This ramp does not

support robust

BOD

tPOFF must be

satisfied.

Applies to ramp up

and ramp down

High-voltage BOD (HV BOD) specifications

SID500

VTR_2P7_R

HVBOD2.7Vtrimmedrisingtrippoint

for VDDD and VDDA_ADC (default)

2.474

2.55

2.627

SID501

VTR_2P7_F

HV BOD 2.7 V trimmed falling trip

point for VDDD and VDDA_ADC (default)

2.449

2.525

2.601

SID502

VTR_3P0_R

HVBOD3.0Vtrimmedrisingtrippoint

for VDDD and VDDA_ADC

2.765

2.85

2.936

SID503

VTR_3P0_F

HV BOD 3.0 V trimmed falling trip

point for VDDD and VDDA_ADC

2.74

2.825

2.91

SID505

HVBOD_RR_A Power ramp rate: VDDD and VDDA_ADC

(Active)

––

100

mV/µs

SID506

HVBOD_RR_D

Power ramp rate: VDDD and VDDA_ADC

(DeepSleep)

––

mV/µs

SID507

tDLY_ACT_HVBOD Active mode delay between VDDD

falling/rising through VTR_2P7_F/R or

VTR_3P0_F/R and an internal HV BOD

output transitioning through VDDD / 2

––

0.5

µs

Guaranteed by

design

SID507A tDLY_ACT_H-

VBOD_A

Active mode delay between VDDA_ADC

falling/rising through VTR_2P7_F/R or

VTR_3P0_F/R and internal HV BOD

output transitioning through VDDD / 2

––

1µs

Guaranteed by

design

SID507B tDLY_DS_HVBOD DeepSleep mode delay between

VDDD/VDDA_ADC falling/rising through

VTR_2P7_F/R or VTR_3P0_F/R and an

internal HV BOD output transitioning

through VDDD /2

––

4µs

Guaranteed by

design

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