MPC821 datasheet(221/242 Pages) NXP

221 / 242 page

Support Information

MOTOROLA

MPC860TFADS Daughter Board Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

GND

I/O, X

MPC’s Data line 5.

GND

I/O, X

MPC’s Data line 4.

GND

I/O, X

MPC’s Data line 3.

GND

I/O, X

MPC’s Data line 2.

GND

I/O, X

MPC’s Data line 1.

GND

I/O, X

MPC’s Data line 0.

GND

DRMH_W~

O, L

Dram Half Word. Sets the Dram to 16 bit data bus width. See

TABLE 4-10. “BCSR1 Description” on page 49. In the

motherboard documentations.

DRAMEN~

O, L

Dram Enable. Enables Dram to the FADS memory map. See

TABLE 4-10. “BCSR1 Description” on page 49. In the

motherboard documentations.

FCFGEN~

O, L

Flash Conﬁguration Enable. Allows for Hard Reset Conﬁguration

to be obtained from the Flash memory provided that this option is

supported

the

MPC.

See

TABLE

4-10.

“BCSR1

Description” on page 49. In the motherboard documentations.

F_EN~

O, L

Flash Enable. Enables the Flash memory to the FADS memory

map. See

TABLE 4-10. "BCSR1 Description" on page 49 In

the motherboard documentations.

SDRAMEN

O, H

Sdram Enable. Enables the Synchronous Dram to the FADS

memory map. See

TABLE 4-10. “BCSR1 Description” on

page 49. In the motherboard documentations.

BCSREN~

O, L

BCSR Enable. Enables the BCSR to the FADS memory map. See

TABLE 4-10. “BCSR1 Description” on page 49. In the

motherboard documentations.

TABLE 5-12. PM4 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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