MPC821 datasheet(222/242 Pages) NXP

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MPC860TFADS Daughter Board Design Specification—Rev 0.1

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

FETHFDE

O, X

Full Duplex Enable when auto negotiation is enable the FDE pin

of the LXT970 determine full duplex advertisement capability in

combination

with

MF4

and

CFG1.

See

than

LXT970

documentation.

When auto negotiation is disable the FDE pin of the LXT970

effects full duplex and determines the value of bit 0.8 Duplex

Mode.

When this pin is high Full Duplex in Enable. 0.8 = 1.

When this pin is low Full Duplex is Disable 0.8 = 0.

PCCEN~

O, L

PC- Card Enable. Enables the PC-Card to be accessed by the

FADS.

EXTOLI0

I/O, X

External Tool Identiﬁcation 0. Connected to BCSR2. See

4•11•4

“BCSR2 - Board Control / Status Register - 2" on page

51.In the motherboard documentations.

SGLAMP~

O, L

Signaling Lamp. Used for misc. s/w signaling purpose. See

TABLE 4-23. “BCSR4 Description” on page 57. In the

motherboard documentations.

EXTOLI2

I/O, X

External Tool Identiﬁcation 2. Connected to BCSR2. See

4•11•4

“BCSR2 - Board Control / Status Register - 2" on page

51.In the motherboard documentations.

USBVCC1

O, X

Applies only for MPC823DB. Reserved Signal for USB Power.

See

TABLE 4-23. “BCSR4 Description” on page 57. In the

motherboard documentations.

DBREV0

I, X

Daughter Board Revision Code Signal 0. The MSB of the D/B

revision Code. See

TABLE 4-13. “BCSR2 Description” on

page 52. In the motherboard documentations.

EXTOLI1

I/O, X

External Tool Identiﬁcation 1. Connected to BCSR2. See

4•11•4

“BCSR2 - Board Control / Status Register - 2" on page 51.

In the motherboard documentations.

DBREV2

I, X

Daughter Board Revision Code Signal 2. The LMSB of the D/B

revision Code. See

TABLE 4-13. “BCSR2 Description” on

page 52. In the motherboard documentations.

EXTOLI3

I/O, X

External Tool Identiﬁcation 3. Connected to BCSR2. See

4•11•4

“BCSR2 - Board Control / Status Register - 2" on page 51.

In the motherboard documentations.

BCSR3R1

I/O, X

Reserved signal 1 in BCSR3. See

TABLE 4-19. “BCSR3

Description” on page 55. In the motherboard documentations.

DBREV1

I/O, X

Daughter Board Revision Code Signal 1. See

TABLE 4-13.

“BCSR2 Description” on page 52. In the motherboard

documentations.

DBID1

I/O, X

Daughter Board ID Code 1. Part of the ﬁeld which designates the

type of daughter board connected. See

TABLE 4-19. “BCSR3

Description” on page 55 In the motherboard documentations.

100

BCSR3R0

I/O, X

Reserved signal 0 in BCSR3. See

TABLE 4-19. “BCSR3

Description” on page 55 In the motherboard documentations.

TABLE 5-12. PM4 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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