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S32K310 bảng dữ liệu(PDF) 103 Page - NXP Semiconductors

tên linh kiện S32K310
Giải thích chi tiết về linh kiện  Supports S32K344, S32K324, S32K314, S32K312, S32K341 and S32K342. Data is preliminary for S32K311, S32K310, S32K328, S32K338, S32K348, S32K358 and S32K388
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S32K310 bảng dữ liệu(HTML) 103 Page - NXP Semiconductors

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12.5 Ethernet characteristics
12.5.1 Ethernet MII (100 Mbps)
The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/
constraints for the physical interface. Measurements are with maximum output load of 25pF, input transition of 1ns and pad
configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V.
Table 45. Ethernet MII (100 Mbps)
Symbol
Description
Min
Typ
Max
Unit
Condition
Spec
Number
—
RXCLK frequency
—
—
25
MHz
—
—
MII1
RXCLK pulse width
high
35
—
65
%RXCLK
period
—
—
MII2
RXCLK pulse width
low
35
—
65
%RXCLK
period
—
—
MII3
RXD[3:0], RXDV,
RXER to RXCLK
setup
5
—
—
ns
—
—
MII4
RXCLK to RXD[3:0],
RXDV, RXER hold
5
—
—
ns
—
—
tCYC_TX
TXCLK frequency
—
25
—
MHz
—
—
MII5
TXCLK pulse width
high
35
—
65
%TXCLK
period
—
—
MII6
TXCLK pulse
width low
35
—
65
%TXCLK
period
—
—
MII7
TXCLK to TXD[3:0],
TXEN, TXER invalid
2
—
—
ns
—
—
MII8
TXCLK to TXD[3:0],
TXEN, TXER valid
—
—
25
ns
—
—
NXP Semiconductors
Communication interfaces
S32K3xx Data Sheet, Rev. 5.2, 10/2022
Data Sheet: Technical Data
Preliminary Information
103 / 137



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