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MCIMX503CVM8B bảng dữ liệu(PDF) 74 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  i.MX50 Applications Processors for Consumer Products
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i.MX50 Applications Processors for Consumer Products, Rev. 7
Electrical Characteristics
Freescale Semiconductor
74
4.9.2.1
CSPI Master Mode Timing
Figure 32 depicts the timing of CSPI in master mode and Table 50 lists the CSPI master mode timing
characteristics.
Figure 32. CSPI Master Mode Timing Diagram
Table 50. CSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
CSPIx_CLK Cycle Time
tclk
60
—
ns
CS2
CSPIx_CLK High or Low Time
tSW
6—
ns
CS3
CSPIx_CLK Rise or Fall
tRISE/FALL
——
ns
CS4
CSPIx_CS_x pulse width
tCSLH
15
—
ns
CS5
CSPIx_CS_x Lead Time (CS setup time)
tSCS
5—
ns
CS6
CSPIx_CS_x Lag Time (CS hold time)
tHCS
5—
ns
CS7
CSPIx_DO Setup Time
tSmosi
5—
ns
CS8
CSPIx_DO Hold Time
tHmosi
5—
ns
CS9
CSPIx_DI Setup Time
tSmiso
5—
ns
CS10
CSPIx_DI Hold Time
tHmiso
5—
ns
CS11
CSPIx_DRYN Setup Time
tSDRY
5—
ns
CS1
CS7 CS8
CS2
CS2
CS4
CS6
CS5
CS9 CS10
CSPIx_CLK
CSPIx_CS_x
CSPIx_DO
CSPIx_DI
CSPIx_DRYN1
CS11
CS3
CS3



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