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MCIMX503CVM8B bảng dữ liệu(PDF) 30 Page - NXP Semiconductors

tên linh kiện MCIMX503CVM8B
Giải thích chi tiết về linh kiện  i.MX50 Applications Processors for Consumer Products
PDF  136 Pages
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MCIMX503CVM8B bảng dữ liệu(HTML) 30 Page - NXP Semiconductors

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i.MX50 Applications Processors for Consumer Products, Rev. 7
Electrical Characteristics
Freescale Semiconductor
30
4.2.1
Power-Up Sequence
Figure 2 shows the power-up sequence.
Figure 2. Power-Up Sequence
NOTE
1) The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail is at its working voltage.
2) No power-up sequence dependencies exist between the supplies shown
shaded in gray.
4.2.2
Power-Down Sequence
The power-down sequence is recommended to be the opposite of the power-up sequence. In other words,
the same power supply constraints exist while powering off as while powering on.
4.2.3
Resume Sequence
When the i.MX50 is resuming from STOP mode, there are some special sequencing considerations. The
resume timing is determined by the following internal counters:
1. STBY_COUNT. This register is in the CCM block and may be set to a maximum of 16 x 32 kHz
cycles, or 500
μsec.



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