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MCIMX503CVM8B bảng dữ liệu(PDF) 57 Page - NXP Semiconductors |
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MCIMX503CVM8B bảng dữ liệu(HTML) 57 Page - NXP Semiconductors |
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57 / 136 page ![]() Electrical Characteristics i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 57 4.6.5.3 Samsung Toggle Mode AC Timing 4.6.5.3.1 Command and Address Timing NOTE Samsung Toggle Mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. Please refer to the above chapter for details. NF24 postamble delay tPOST POST_DELAY*tCK —ns NF25 CLE and ALE setup time tCALS 0.5*tCK —ns NF26 CLE and ALE hold time tCALH 0.5*tCK —ns NF27 Data input to first DQS latching transition tDQSS tCK —ns 1 GPMI’s sync mode output timing could be controlled by module’s internal register, say HW_GPMI_TIMING2_CE_DELAY, HW_GPMI_TIMING_PREAMBLE_DELAY, and HW_GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers’ setting. In the above table, we use CE_DELAY/PRE_DELAY/POST_DELAY representing these settings each. Table 41. Source Synchronous Mode Timing Parameters1 (continued) ID Parameter Symbol Timing T = GPMI Clock Cycle Unit Min. Max. |
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