P5021 datasheet(149/155 Pages) NXP

149 / 155 page

Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

149

In the RCW configuration field for each bank SRDS_LPD_Bn with unused lanes, the respective bit for each unused lane must

be set to power down the lane.

3.6.4

USB controller connections

This section details the hardware connections required for the USB controllers.

3.6.4.1

USB divider network

This figure shows the required divider network for the VBUS interface for the chip. Additional requirements for the external

components are as follows:

•

Both resistors require 0.1% accuracy and a current capability of up to 1 mA. They must both have the same temperature

coefficient and accuracy.

•

The zener diode must have a value of 5 V

−5.25 V.

•

The 0.6 V diode requires an IF = 10 mA, IR < 500 nA and VF(Max) = 0.8 V.

Figure 61. Divider network at VBUS

USB1_DRVVBUS and USB1_PWRFAULT are muxed on GPIO[4:5] pins, respectively. USB2_DRVVBUS and

USB2_PWRFAULT are muxed on GPIO[6:7] pins, respectively. Setting the RCW[GPIO] bit selects USB functionality on the

GPIO pins.

3.6.4.2

USBn_VDD_1P8_DECAP capacitor options

he USBn_VDD_1P8_DECAP pins require a capacitor connected to GND. This table list the recommended capacitors for the

USBn_VDD_1P8_DECAP signal.

Table 107. Recommended capacitor parts for USBn_VDD_1P8_DECAP

Manufacturer

Part Number

Value

ESR

Package

Kemet

T494B105(1)025A(2)

μF, 25 V

B(3528)

T494B155(1)025A(2)

1.5

μF, 25 V

1.5

—

NIC

NMC0603X7R106KTRPF

μF, 10 V

Low ESR

0603

TDK Corporation

CERB2CX5R0G105M

μF, 4 V

200 m-

0603

Vishay

TR3B105(1)035(2)1500

μF, 35 V

1.5

B(3528)

USBn_DRVVBUS

18.1 k

USBn_VBUS_CLMP

51.2 k

Chip

5 VZ

0.6 VF

USBn_PWRFAULT

VBUS Charge

Pump

VBUS

(USB Connector)

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