P5021 datasheet(69/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

2.9.2

DDR3 and DDR3L SDRAM interface AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports

DDR3 and DDR3L memories. Note that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the

required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.

2.9.2.1

DDR3 and DDR3L SDRAM interface input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.

Table 22. DDR3 SDRAM interface input AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

> 1200 MT/s data rate

VILAC

—

MVREF – 0.150

—

≤ 1200 MT/s data rate

MVREF – 0.175

AC input high voltage

> 1200 MT/s data rate

VIHAC

MVREF + 0.150

—

≤ 1200 MT/s data rate

MVREF + 0.175

Table 23. DDR3L SDRAM interface input AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

> 1067 MT/s data rate

VILAC

—

MVREF – 0.135

—

≤ 1067 MT/sdata rate

MVREF – 0.160

AC input high voltage

> 1067 MT/s data rate

VIHAC

MVREF + 0.135

—

≤ 1067 MT/s data rate

MVREF + 0.160

Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC

tCISKEW

1600 MT/s data rate

–112

112

1333 MT/s data rate

–125

125

1200 MT/s data rate

–147.5

147.5

1066 MT/s data rate

–170

170

800 MT/s data rate

–200

200

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