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P5021 bảng dữ liệu(PDF) 70 Page - NXP Semiconductors

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P5021 bảng dữ liệu(HTML) 70 Page - NXP Semiconductors

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor
70
This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram
Tolerated Skew for MDQS—MDQ/MECC
tDISKEW
ps
2
1600 MT/s data rate
–200
200
1333 MT/s data rate
–250
250
1200 MT/s data rate
–275
275
1066 MT/s data rate
–300
300
800 MT/s data rate
–425
425
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW =±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n]
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
tDISKEW



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