P5021 datasheet(147/155 Pages) NXP

147 / 155 page

Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

147

Figure 60. Aurora 70 pin connector duplex interface connection

PORESET

From Target

Board Sources

RESET

HRESET

VIO VSense2

1 k

COP_TMS

COP_TDO

COP_TDI

COP_TCK

TMS

TDO

TDI

TRST

42,47,48,53,54,

29,30,35,36,41,

(if any)

Notes:

TRST1

10 k

Duplex 70

HRESET

2. Populate this with a 1 k

Ω resistor for short-circuit/current-limiting protection.

OVDD

10 k

PORESET1

in order to fully control the processor as shown here.

1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor

TCK

3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing

to position B.

10 k

4. Asserting HRESET causes a hard reset on the device.

to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed

Vendor I/O 3 N/C

Vendor I/O 2 (Aurora Event Out)

Vendor I/O 1 (Aurora Event In)

Vendor I/O 0 (Aurora HALT)

5,11,17,23,24,

EVT[4]

EVT[1]

EVT[0]

TX0_P

TX0_N

SD_TX09_P

SD_TX09_N

TX1_P

TX1_N

SD_TX08_P

SD_TX08_N

RX0_P

RX0_N

SD_RX09_P

SD_RX09_N

RX1_P

RX1_N

SD_RX08_P

SD_RX08_N

Vendor I/O 5 (Aurora HRESET)

Vendor I/O 4 N/C

EVT[4]

31,33,37,38,

N/C

39,40,43,44,

45,46,49,50,

51,52,55,56,

57,58,61,62,

63,64,67,68,

25,26,27,28,

69,70

59,60,65,66

Connector

Physical Pinout

10 k

Chip

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