P5021 datasheet(137/155 Pages) NXP

137 / 155 page

Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

137

3.3

Power supply design

3.3.1

PLL power supply filtering

Each of the PLLs described in Section 3.1, “System clocking,” is provided with power through independent power supply pins

(AVDD_PLAT, AVDD_CCn, AVDD_DDR, AVDD_FM, and AVDD_SRDSn). AVDD_PLAT, AVDD_CCn, AVDD_FM, and AVDD_DDR

voltages must be derived directly from the VDD_PL source through a low frequency filter scheme. AVDD_SRDSn voltages must

be derived directly from the SVDD source through a low frequency filter scheme.

The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in

Figure 51, one for each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection

from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range.

Table 106. I/O voltage selection

Signals

Value

(binary)

VDD voltage selection

BVDD

CVDD

LVDD

IO_VSEL[0:4]

Default (0_0000)

0_0000

3.3 V

0_0001

3.3 V

2.5 V

0_0011

3.3 V

2.5 V

3.3 V

0_0100

3.3 V

2.5 V

0_0110

3.3 V

1.8 V

3.3 V

0_0111

3.3 V

1.8 V

2.5 V

0_1001

2.5 V

3.3 V

0_1010

2.5 V

3.3 V

2.5 V

0_1100

2.5 V

3.3 V

0_1101

2.5 V

0_1111

2.5 V

1.8 V

3.3 V

1_0000

2.5 V

1.8 V

2.5 V

1_0010

1.8 V

3.3 V

1_0011

1.8 V

3.3 V

2.5 V

1_0101

1.8 V

2.5 V

3.3 V

1_0110

1.8 V

2.5 V

1_1000

1.8 V

3.3 V

1_1001

1.8 V

2.5 V

1_1011

3.3 V

1_1100

3.3 V

1_1101

3.3 V

1_1110

3.3 V

1_1111

3.3 V

All Others

Reserved

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