P5021 datasheet(136/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Hardware design considerations

Freescale Semiconductor

136

3.1.8

Frame Manager (FMan) clock select

The Frame Managers (FM) can each be synchronous with or asynchronous to the platform, depending on configuration.

This table describes the clocking options that may be applied to each FM. The clock selection is determined by the binary value

of the RCW Clocking Configuration fields FM1_CLK_SEL and FM2_CLK_SEL.

3.2

Supply power default setting

This chip is capable of supporting multiple power supply levels on its I/O supplies. The I/O voltage select inputs, shown in the

following table, properly configure the receivers and drivers of the I/Os associated with the BVDD, CVDD, and LVDD power

planes, respectively.

WARNING

Incorrect voltage select settings can lead to irreversible device damage.

Table 105. Frame Manager (FMan) clock select

Binary value of FMn_CLK_SEL

FM frequency

0b0

Platform Clock Frequency /2

0b1

FMan PLL Frequency /2 1,2

Notes:

1. For asynchronous mode, max frequency see Table 94.

2. For PLL settings, see Table 96.

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