PMS232 datasheet(35/94 Pages) PADAUK

35 / 94 page

PMC232/PMS232 Series

12-bit ADC Enhanced FPPA

8-bit OTP Controller

Page 35 of 94

PDK-DS-PMx232_V104– Dec. 18, 2018

5-5. Data Memory -- SRAM

Fig. 7 shows the SRAM data memory organization of PMC232/PMS232, all the SRAM data memory could be

accessed by FPP0 and FPP1 directly with 1T clock cycle, the data access can be byte or bit operation.

Besides data storage, the SRAM data memory is also served as data pointer of indirect access method and the

stack memory for all FPP units.

The stack memory for each processing unit should be independent from each other, and defined in the data

memory. The stack pointer is defined in the stack pointer register of each processing unit; the depth of stack

memory of each processing unit is defined by the user. The arrangement of stack memory fully flexible and can

be dynamically adjusted by the user.

For indirect memory access mechanism, the data memory is used as the data pointer to address the data byte.

All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory access.

Since the data width is 8-bit, all the 160 bytes data memory of PMC232/PMS232 can be accessed by indirect

access mechanism.

Fig.7: Data Memory Organization

5-6. Arithmetic and Logic Unit

Arithmetic and Logic Unit (ALU) is the computation element to operate integer arithmetic, logic, shift and other

specialized operations. The operation data can be from instruction, accumulator or SRAM data memory.

Computation result could be written into accumulator or SRAM. FPP0 and FPP1 will share ALU for its

corresponding operation.

DATA

index

FPP0 stack

DATA

FPP1 stack

DATA

FPP0

FPP1

Address

000h

9Fh

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