PMS232 datasheet(18/94 Pages) PADAUK

18 / 94 page

PMC232/PMS232 Series

12-bit ADC Enhanced FPPA

8-bit OTP Controller

Page 18 of 94

PDK-DS-PMx232_V104– Dec. 18, 2018

Symbol

Description

Min

Typ

Max

Unit

Conditions (Ta=25

oC)

fILRC

Frequency of ILRC *

20.4*

24*

27.6*

KHz

VDD=5.0V, Ta=25

15.6*

16.8*

24*

32.4*

31.2*

VDD=5.0V, -40

oC <Ta<85oC*

VDD=5.0V, -20

oC <Ta<70oC*

10.2*

12*

13.8*

VDD=3.3V, Ta=25

4.55*

4.90*

9.45*

9.10*

VDD=2.2V, -40

oC <Ta<85oC*

VDD=2.2V, -20

oC <Ta<70oC*

tINT

Interrupt pulse width

VDD = 5.0V

VADC

Supply voltage for workable ADC

2.5

5.0

VAD

AD Input Voltage

VDD

ADrs

ADC resolution

bit

ADcs

ADC current consumption

0.9

0.8

@5V

@3V

ADclk

ADC clock period

2.5V ~ 5.5V

tADCONV

ADC conversion time

(TADCLK is the period of the selected

AD conversion clock)

TADCLK

12-bit resolution

AD DNL ADC Differential Non-Linearity

±2*

LSB

AD INL

ADC Integral Non-Linearity

±4*

LSB

ADos

ADC offset*

VDR

RAM data retention voltage*

1.5

PMC232/PMS232 in stop

mode.

R(VDD/2)

(VDD/2) pull-up / pull-down resistance

2.5

KΩ

ΔV

(VDD/2)

Deviation of (VDD/2) output voltage

±1%

±3%

@VDD=5V

tWDT

Watchdog timeout period

2408

TILRC

misc[1:0]=00 (default)

4096

misc[1:0]=01

16384

misc[1:0]=10

256

misc[1:0]=11

tWUP

System wake-up period

Fast wake-up by IO toggle from

STOPEXE suspend

128

TSYS

Where TSYS is the time period

of system clock

Fast wake-up by IO toggle from

STOPSYS suspend, IHRC is the system

clock

128

TSYS

Since IHRC starts up more

quickly in the beginning, so

the actual wake-up time will be

shorter than standard 128

Sysclk

Fast wake-up by IO toggle from

STOPSYS suspend, ILRC is the system

clock

128

TSYS

Where TSYS is ILRC-based

time period of system clock

Normal wake-up from STOPEXE or

STOPSYS suspend

1024

TILRC

Where TILRC is the clock

period of ILRC

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