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PMS232 bảng dữ liệu(PDF) 34 Page - PADAUK Technology. |
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PMS232 bảng dữ liệu(HTML) 34 Page - PADAUK Technology. |
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34 / 94 page ![]() PMC232/PMS232 Series 12-bit ADC Enhanced FPPA TM 8-bit OTP Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 34 of 94 PDK-DS-PMx232_V104– Dec. 18, 2018 5-4. Boot Procedure POR (Power-On-Reset) is used to reset PMC232/PMS232 when power up, however, the supply voltage may be not stable. To ensure the stability of supply voltage after power up, it will wait 1024 ILRC clock cycles before first instruction being executed, which is tSBP and shown in the Fig. 5. After boot up procedure, the default system clock is ILRC; user should ensure that the power should be stable after boot up time. VDD POR Program Execution tSBP Boot up from Power-On Reset Fig.5: Power-Up Sequence Fig. 6 shows the typical program flow after boot up. Please notice that the FPP1 is disabled after reset and recommend NOT enabling FPP1 before system and FPP0 initialization. Start Initialize the system Initialize the I/O Initialize the shared Resources Set the Stack of FPP0 Enable FPP1 Set the Stack of FPP1 FPP1 Firmware FPP0 Firmware FPP1 FPP0 Fig.6: Boot Procedure |
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