PMS232 datasheet(43/94 Pages) PADAUK

43 / 94 page

PMC232/PMS232 Series

12-bit ADC Enhanced FPPA

8-bit OTP Controller

Page 43 of 94

PDK-DS-PMx232_V104– Dec. 18, 2018

5-9. 8-bit Timer (Timer2) with PWM generation

An 8-bit hardware timer (Timer2) with PWM generation is implemented in the PMC232/PMS232, please refer

to Fig. 10 shown its hardware diagram, the clock sources of Timer2 may come from system clock, internal high

RC oscillator (IHRC), internal low RC oscillator (ILRC), PA0, PA3 and PA4, bit [7:4] of register tm2c are used to

select the clock of Timer2. Please notice that external crystal oscillator is NOT to be the clock of Timer2

because of possible clock glitch. If IHRC is selected for Timer2 clock source, the clock sent to Timer2 will keep

running when using ICE in halt state. According to the setting of register tm2c[3:2], Timer2 output can be

selectively output to PA2 or PA3. At this point, regardless of whether PA2 or PA3 is the input or output state,

Timer2 signal will be forced to output. A clock pre-scaling module is provided with divided-by-1, 4, 16, and 64

options, controlled by bit [6:5] of tm2s register; one scaling module with divided-by-1~31 is also provided and

controlled by bit [4:0] of tm2s register. In conjunction of pre-scaling function and scaling function, the frequency

of Timer2 clock (TM2_CLK) can be wide range and flexible. TM2_CLK can be selected as system clock in

order to provide special frequency of system clock, please refer to clkmd register.

The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back by

tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound

modes for Timer2: period mode and PWM mode; period mode is used to generate periodical output waveform

or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-bit or 8-bit PWM

resolution, Fig. 11 shows the timing diagram of Timer2 for both period mode and PWM mode.

Fig.11: Timer2 hardware diagram

tm2c[7:4]

CLK,

IHRC,

ILRC,

PA0,

~PA0,

PA3,

~PA3,

PA4,

~PA4

Pre-

scalar

1, 4,

16, 64

tm2s[6:5]

Scalar

1 ~ 31

tm2s[4:0]

8-bit

counter

upper

bound

tm2b[7:0]

tm2c.1

PA2

PA3

tm2c[3:2]

tm2c.0

tm2ct[7:0]

edge to

interrupt

tm2s.7

TM2_CLK

PMS232 bảng dữ liệu(PDF) 43 Page - PADAUK Technology.

PMS232 bảng dữ liệu(HTML) 43 Page - PADAUK Technology.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

bảng dữ liệu tải về

Link URL