PMS232 datasheet(3/94 Pages) PADAUK

3 / 94 page

PMC232/PMS232 Series

12-bit ADC Enhanced FPPA

8-bit OTP Controller

Page 3 of 94

PDK-DS-PMx232_V104– Dec. 18, 2018

Table of content

1. Features ............................................................................................................................. 9

1-1.Special Features ....................................................................................................................9

1-2. System Functions ..................................................................................................................9

1-3. High Performance RISC CPU Array.......................................................................................9

1-4. Package Information ............................................................................................................10

2. General Description and Block Diagram ...................................................................... 11

3. Pin Assignment and Description................................................................................... 12

4. Device Characteristics ................................................................................................... 17

4-1. AC/DC Device Characteristics .............................................................................................17

4-2. Absolute Maximum Ratings .................................................................................................19

4-3. Typical ILRC frequency vs. VDD and temperature...............................................................20

4-4. Typical IHRC frequency deviation vs. VDD and temperature (calibrated to 16MHz).............21

4-5. Typical operating current vs. VDD @ system clock = ILRC/n...............................................22

4-6. Typical operating current vs. VDD @ system clock = IHRC/n ..............................................22

4-7. Typical operating current vs. VDD @ system clock = 4MHz EOSC / n.................................23

4-8. Typical operating current vs. VDD @ system clock = 32kHz EOSC / n ................................23

4-9. Typical IO driving current (IOH) and sink current (IOL) ............................................................24

4-10. Typical IO input high/low threshold voltage (VIH/VIL) ...........................................................24

4-11. Typical resistance of IO pull high device ............................................................................25

4-12. Typical VDD/2 Bias output voltage.....................................................................................25

4-13. Typical power down current (IPD) and power save current (IPS)...........................................26

4-14. Timing charts for boot up conditions ..................................................................................27

5. Functional Description................................................................................................... 28

5-1. Processing Units..................................................................................................................28

5-1-1. Program Counter .......................................................................................................29

5-1-2. Stack Pointer .............................................................................................................29

5-1-3. Single FPP mode.......................................................................................................30

5-2. Program Memory - OTP.......................................................................................................31

5-2-1. Program Memory Assignment....................................................................................31

5-2-2. Example of Using Program Memory for Two FPP mode ............................................32

5-2-3. Example of Using Program Memory for Single FPP mode.........................................32

5-3. Program Structure ...............................................................................................................33

5-3-1. Program structure of two FPP units mode .................................................................33

5-3-2. Program structure of single FPP mode ......................................................................33

5-4. Boot Procedure....................................................................................................................34

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