TLE9461ES datasheet(100/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

Serial Peripheral Interface

Datasheet

100

Rev.1.1

2019-09-27

Certain SPI control bits used to configure device functionality can be locked to avoid unintentional bit

modification. The respective bit type is ‘rwl’. There are two levels of configuration locks:

• CFG_LOCK_0 in the HW_CTRL_1 is the level 0 lock mechanism: The bits CP_EN and GPIO can be locked.

In case the configuration must be changed then CFG_LOCK_0 must be cleared first

• CFG_LOCK_1 in the HW_CTRL_2 is the level 1 lock mechanism: All other lockable bits with the type ‘rwl’

are locked and can only be modified at the next device power up

No status information can be lost, even if a bit changes right after the first 7 SPI clock cycles before the SPI

frame ends. In this case the status information field is updated with the next SPI command. However, the flag

is already set in the relevant status register.

The SBC status information from the SPI status registers is transmitted in a compressed format with each SPI

response on SDO in the so-called Status Information Field register (see also Figure 40). The purpose of this

microcontroller only needs to read registers which have changed.

Each bit in the Status Information Field represents a SPI status register (see Table 26). As soon as one bit is set

in one of the status registers, the corresponding bit in the Status Information Field register is set. Only the

most important registers are represented in the Status Information Field, e.g. the register WK_LVL_STAT is

not included.

For example if bit 0 in the Status Information Field is set to ‘1’, one or more bits of the register 100 0001

(SUP_STAT_0) are set to 1. Then this register needs to be read with a second SPI command. The bit in the

Status Information Field is set to 0 when all bits in the register 100 0001 have been reset to ‘0’.

Table 26

Status Information Field

Bit in Status

Information Field

Corresponding

Address Bit

Status Register Description

100 0001

SUP_STAT_0 - Supply Status: POR, VCC2 fail, VCC1 fail

100 0010

THERM_STAT - Thermal Protection Status

100 0011

DEV_STAT- Device Status: Mode before wake-up-

up/failure, WD Fail, SPI Fail, Failure

100 0100

BUS_STAT - Bus Failure Status: CAN;

100 0110

100 0111

WK_STAT_0, WK_STAT_1 - Wake Source Status;

Status bit is a combinational OR of both registers

100 0000

SUP_STAT_1: VS_UV, VCC1_WARN/OV

101 0100

GPIO_OC_STAT: GPIO over current

101 0101

GPIO_OL_STAT: GPIO open load

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