TLE9461ES datasheet(28/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

System Features

Datasheet

Rev.1.1

2019-09-27

Note:

An over voltage event at VCC1 leads to SBC Restart Mode only if the bit VCC1_OV_RST is set and if

CFG0_STATE = ‘1’ (Config 1/3).

Note:

The content of the WD_FAIL bits depends on the device configuration, e.g. 1 or 2 watchdog failures.

5.1.6

SBC Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning Off the VCC1

supply and powering Off the microcontroller. After a wake-up event the system restarts again.

The Fail-Safe Mode is automatically entered after following events:

• SBC thermal shutdown (TSD2) (see also Chapter 12.8.3),

• over voltage on VCC1 if the bit VCC1_OV_RST is set and if CFG0_STATE = ‘0’,

• 1st incorrect watchdog trigger in Config2 (CFG1 = 1) and after a 2nd incorrect watchdog trigger in Config4

(CFG1 = 0) (see also Chapter 5.1.1),

•

VCC1 is shorted to GND (see also Chapter 12.6),

In this case, the default wake sources CAN, WK/VSENSE and FO/GPIO (if configured as wake input - see also

registers BUS_CTRL_0, WK_CTRL_1 and GPIO_CTRL) are activated, the previous wake-up events are cleared

in the register WK_STAT_0 and WK_STAT_1, and both voltage regulators and the GPIO - if configured as HS or

LS - are switched Off.

The SBC Fail-Safe Mode is entered regardless of the FO/GPIO pin configuration. If WK/VSENSE and FO/GPIO are

configured for the alternative measurement function (WK_MEAS = 1) then these pins keep their configuration

for the measurement function when SBC Fail-Safe Mode is entered, i.e. they are not automatically activated

as wake sources.

The SBC Fail-Safe Mode is maintained until a wake-up event on the default wake sources occurs. To avoid any

fast toggling behavior a filter time of typ. 100ms (tFS,min) is implemented. Wake-up events during this time is

stored and automatically lead to SBC Restart Mode after the filter time.

In case of a VCC1 over temperature shutdown (TSD2), the SBC Restart Mode is entered automatically after a

filter time of typ. 1s (tTSD2) (without the need of a wake-up event) once the device temperature has fallen below

the TSD2 threshold. Please see Chapter 12.8.3 on how to extend the minimum TSD2 waiting time.

Leaving the SBC Fail-Safe Mode does not result in a deactivation of the Fail Output pins.

The following functions are controlled by the C Fail-Safe Mode:

• FO output (if configured as FO) is activated (see also Chapter 11)

• VCC1 is switched Off

• VCC2 is switched Off

• CAN is set to Wake Capable

• GPIO behavior:

– if configured as HS or LS: it is switched Off

– if configured as wake input: it is set to wake capable in Static Sense mode

• WK/VSENSE pin is set to wake capable in Static Sense mode (only if WK_MEAS = 0)

• Cyclic Sense and Cyclic Wake is disabled

• SPI communication is disabled because VCC1 is Off, RSTN and digital I/O pins are pulled Low

• The Fail-Safe Mode activation is signalled in the SPI register DEV_STAT with the bits FAILURE and

DEV_STAT

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