TLE9461ES datasheet(77/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

Fail Output (FO) and General Purpose I/O (GPIO)

Datasheet

Rev.1.1

2019-09-27

– The switch is controlled by the PWM generator: 0% DC = Off and 100% DC = On;

any other duty cycle can be configured in PWM_CTRL.

The PWM frequency can be selected in PWM_FREQ_CTRL

– The respective level at the pin is shown in WK_LVL_STAT in SBC Normal, Stop-, Init and Restart Mode

and can serve as a feedback about the respective switch state1)

– On-state open load detection and overcurrent shutdown is implemented.

During PWM operation the diagnosis is active only during the HS On-time.

In case of open load detection the bit GPIO_OL is set.

In case of over current detection the bit GPIO_OC is set and the switch is shut down.

Depending on the duty cycle the diagnosis might not be activated considering the respective filter time

• High-Side with Cyclic Sense functionality when configured as GPIO = ‘011’:

– The HS is used in combination with the WK pin and is controlled by the Timer. Cyclic Sense does not

work if the GPIO is not configured accordingly.

– The configuration for Cyclic Sense, e.g. the period and On-time of the Cyclic Sense function is done via

the registers TIMER_CTRL, WK_CTRL_1, WK_PUPD_CTRL

– A learning cycle is always started if the timer is started via the On-time and GPIO is configured as HS

with Cyclic Sense = ‘011’

– Overcurrent shutdown is active only during the HS On-time:

In case of over current detection the bit GPIO_OC is set and the switch is shut down.

The timer keeps running, i.e. Cyclic Wake is still available.

The open load detection is not available in this configuration.

– WK_LVL_STAT is not updated

–See Chapter 5.2.1 and Chapter 9.2 for more information about Cyclic Sense

Note:

It must be ensured that the correct GPIO configuration is selected after device power-up to ensure

proper functionality.

It is recommended to use the CFG_LOCK_0 bit to avoid unintentional configuration changes.

It is not recommended to change the GPIO configuration during the operation to avoid misleading

SPI status bit settings (e.g. wake-up event, over current, open load ) or unexpected timings due to

shared PWM generator.

Note:

Before GPIO is be configured as HS or LS with PWM Control the PWM_CTRL register must be set .

Note:

The internally stored default value used for the wake-input configuration is ‘Low’. A level change is

signalized via the bit GPIO_WK_WU in case the externally connected signal on FO/GPIO is ‘High’. If

there is a level change at the FO/GPIO pin while configuring the wake function then a wake-up event

can occur as there is no internal learning cycle and the last filtered value is used as a reference.

Shutdown behavior in case of low-side or high-side configuration (incl. Cyclic Sense & PWM):

• The switch is disabled in case of over current detection with low- or high-side configuration, SBC Restart

or Fail-Safe Mode entry

• The SPI bits are set to GPIO = Off = ‘100’

• The switch stays Off until it is enabled again via the GPIO bits,

•In case CFG_LOCK_0 is set, then the bit must first be cleared before the configuration can be enabled

again. Then the lock bit should be set again

• The switch can be enabled even if GPIO_OL or GPIO_OC bit is set.

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