TLE9461ES datasheet(99/140 Pages) INFINEON

99 / 140 page

TLE9461ES

Lite CAN SBC Family

Serial Peripheral Interface

Datasheet

Rev.1.1

2019-09-27

Note:

In order to read the SPI ERR flag properly, CLK must be Low when CSN is triggered, i.e. the ERR bit is

not valid if the CLK is High on a falling edge of CSN

The number of received SPI clocks is not 0, 16 or 32:

The number of received input clocks is supervised to be 0 or 16 clock cycles and the input word is discarded in

case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was High

during CSN edges. Both errors - 0 or 16 bit CLK mismatch or CLK High during CSN edges - are flagged in the

following SPI output by a “High” at the data output (SDO pin, bit ERR) before the first rising edge of the clock

is received. The complete SPI command is ignored in this case.

RSTN is Low and SPI frames are being sent at the same time:

The ERR flag is set when the RSTN pin is triggered (during SBC Restart) and SPI frames are being sent to the

SBC at the same time. The behavior of the ERR flag is signalized at the next SPI command for below conditions:

• if the command begins when RSTN is High and it ends when RSTN is Low,

• if a SPI command is sent while RSTN is Low,

• If a SPI command begins when RSTN is Low and it ends when RSTN is High.

and the SDO output behaves as follows:

• always when RSTN is Low then SDO is High,

• when a SPI command begins with RSTN is Low and ends when RSTN is High, then the SDO should be

ignored because wrong data is sent.

Note:

It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled

Low and SDO is observed - no SPI Clocks are sent in this case

Note:

The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because the SPI

communication is stopped immediately.

13.3

SPI Programming

For the TLE9461ES, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read Only

and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the actual

configuration and status information, 8 data bits (BIT15...8) are used.

Writing, clearing and reading is done byte wise. The SPI status bits are not cleared automatically and must be

cleared by the microcontroller, e.g. if the TSD2 was set due to over temperature. Some of the configuration

bits will automatically be cleared by the SBC - please refer to the respective register descriptions for detailed

information. In SBC Restart Mode, the device ignores all SPI communication, i.e. it does not interpreted it.

There are two types of SPI registers:

• Control registers: These registers are used to configure the SBC, e.g. SBC mode, watchdog trigger, etc.

• Status registers: These registers indicate the status of the SBC, e.g. wake-up events, warnings, failures, etc.

For the status registers, the requested information is given in the same SPI command in the data out (SDO).

For the control registers, the status of each byte is shown in the same SPI command as well. However,

configuration changes of the same register are only shown in the next SPI command (configuration changes

inside the SBC become valid only after CSN changes from Low to High).

Writing of control registers is possible in SBC Init and Normal Mode. During SBC Stop Mode only the change to

SBC Normal Mode and triggering the watchdog is allowed as well as reading and clearing the status registers.

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