TLE9461ES datasheet(64/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

High-Speed CAN FD Transceiver

Datasheet

Rev.1.1

2019-09-27

Transmitted Recessive bit

width

(CAN FD up to 5Mbps)

tbit(BUS)

155

–

210

CAN Normal Mode;

CL = 100pF;

RL = 60 Ω;

VCAN = 5 V;

CRXD = 15 pF;

tbit(TXD) = 200ns;

Parameter definition

in according to

Figure 24.

P_9.3.46

Receiver timing symmetry

(CAN FD up to 5Mbps)

∆tRec

-45

–

CAN Normal Mode;

CL = 100pF;

RL = 60Ω;

VCAN = 5V;

CRXD = 15pF;

tbit(TXD) = 200ns;

Parameter definition

in according to

Figure 24.

P_9.3.47

TXDCAN Permanent

Dominant Time-out

tTXDCAN_TO 1.6

2.0

2.4

8)CAN Normal Mode

P_9.3.39

BUS Permanent Dominant

Time-out

tBUS_CAN_TO 2.0

2.5

3.0

8)CAN Normal Mode

P_9.3.40

Timeout for bus inactivity

tSILENCE

0.6

–

1.2

P_9.3.48

Bus Bias reaction time

tBias

–

250

µs

P_9.3.49

1) Not subject to production test, specified by design, S2P - Method; f = 10 MHz.

2) VSYM shall be observed during dominant and recessive state and also during the transition dominant to recessive and

vice versa while TXD is simulated by a square signal (50% duty cycle) with a frequency of up to 1 MHz (2 MBit/s);

3) Rtest between (Vs /VCAN) and 0V (GND).

4) Not subject to production test, specified by design.

5) Wake-up is signalized via INTN pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep

Mode.

6) For WUP: time starts with end of last dominant phase of WUP; for WUF: time starts with end of CRC delimiter of the

WUF.

7) ∆tRec=tbit(RXD) -tbit(BUS).

8) Not subject to production test, tolerance defined by internal oscillator tolerance.

Table 18

Electrical Characteristics (cont’d)

Tj = -40°C to +150°C; VS = 5.5 V to 28 V; VCAN = 4.75 V to 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ.

Max.

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