TLE9461ES datasheet(98/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

Serial Peripheral Interface

Datasheet

Rev.1.1

2019-09-27

13.2

Failure Signalization in the SPI Data Output

If the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI

commands are either invalid SBC mode commands or commands which are prohibited by the state machine

to avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set and the

SPI Write command is ignored (mostly no partial interpretation). This bit can be only reset by actively clearing

it via a SPI command.

Invalid SPI commands leading to SPI_FAIL are listed below (in this case the SPI command is ignored):

• Illegal state transitions:

- Going from SBC Stop to SBC Sleep Mode. In this case the SBC enters SBC Restart Mode;

- Trying to go to SBC Stop or SBC Sleep Mode from SBC Init Mode. In this case SBC Normal Mode is entered

• Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored and/or

the new watchdog settings are ignored respectively

• In SBC Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM

settings and HS configuration settings during SBC Stop Mode, etc.;

the SPI command is ignored in this case;

only WD trigger, returning to Normal Mode, triggering a SBC Soft Reset, and Read & Clear status registers

commands are valid SPI commands in SBC Stop Mode;

Note: No failure handling is done for the attempt to go to SBC STOP Mode when all bits in the registers

BUS_CTRL_0 and WK_CTRL_1 are cleared because the microcontroller can leave this mode via SPI

• When entering SBC Stop Mode and WK_STAT_0 and WK_STAT_1 are not cleared; SPI_FAIL is not set but

the INTN pin is triggered

• Changing from SBC Stop to Normal Mode and changing the other bits of the M_S_CTRL register. The other

modifications are ignored

• SBC Sleep Mode: attempt to go to Sleep Mode without any wake source set, i.e. when all bits in the

BUS_CTRL_0, WK_CTRL_0, WK_CTRL_1 and GPIO_CTRL registers are cleared. In this case the SPI_FAIL

bit is set and the device enters SBC Restart Mode.

Even though the Sleep Mode command is not entered in this case, the rest of the command (e.g. modifying

VCC2) is executed but restart values apply during SBC Restart Mode;

Note: At least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,

i.e. the SBC would not be able to wake-up anymore.

If the only wake source is a timer and the timer is Off then the SBC will wake-up immediately from Sleep

Mode and enter Restart Mode;

• Trying to set WK_MEAS when FO/GPIO is not Off, i.e. FO is activated/configured or any GPIO configuration

is selected

• Trying to change the GPIO_CTRL settings in case WK_MEAS is set

• Setting a longer or equal On-time than the timer period of the respective timer

• SDI stuck at High or Low, e.g. SDI received all ‘0’ or all ‘1’

Note:

There is no SPI fail information for unused addresses.

Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 39):

The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set

for following conditions:

• in case the number of received SPI clocks is not 0 or 16

• in case RSTN is Low and SPI frames are being sent at the same time.

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