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TLE9461ES bảng dữ liệu(PDF) 72 Page - Infineon Technologies AG

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Giải thích chi tiết về linh kiện  Lite CAN SBC Family
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TLE9461ES
Lite CAN SBC Family
Interrupt Function
Datasheet
72
Rev.1.1
2019-09-27
In addition to this behavior, INTN is triggered when SBC Stop Mode is entered and not all wake source bits
were cleared in the WK_STAT_0and WK_STAT_1 register.
The SPI status registers are updated at every falling edge of the INTN pulse. All interrupt events are stored in
the respective register (except the register WK_LVL_STAT) until the register is read and cleared via SPI
command. A second SPI read after reading out the respective status register is optional but recommended to
verify that the interrupt event is not present anymore. The interrupt behavior is shown in Figure 29 for class 1
interrupts. The behavior for class 2 is identical.
The INTN pin is also used during SBC Init Mode to select the hardware configuration of the device. See
Chapter 5.1.1 for further information.
Figure 29 Interrupt Signalization Behavior
INTN
WK
CAN
tINT
tINTD
Update of
WK_STAT register
SPI
Read & Clear
Update of
WK_STAT register
WK_STAT
contents
WK
no WK
CAN
no WK
optional
SPI
Read & Clear
WK_STAT
contents
WK + CAN
no WK
No SPI Read & Clear
Command sent



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