DSP56857 datasheet(265/662 Pages) FREESCALE

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SCI Register Descriptions (SCI0_BASE = $1FFFE0 and SCI1_BASE = $1FFDF8)

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-29

10.9.4.3 Receive Data Register Full Flag (RDRF)—Bit 13

This bit is set when the data in the Receive Shift register transfers to the SCI Data register

(SCIDR). Clear RDRF by reading the SCI Status Register (SCISR) with RDRF set and then

reading the SCI Data register in Normal mode or by reading the SCIDR with RDE set.

•

0 = Data not available in SCI Data register

•

1 = Received data available in SCI Data register

10.9.4.4 Receiver Idle Line Flag (RIDLE)—Bit 12

This bit is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1)

appear on the receiver input. Once the RIDLE flag is cleared (the receiver detects a Logic 0), a

valid frame must again set the RDRF flag before an idle condition can set the RIDLE flag.

•

0 = Receiver input is either active now or has never become active since the RIDLE flag

was last cleared

•

1 = Receiver input has become idle (after receiving a valid fame)

Note:

When the Receiver Wake Up (RWU) bit is set, an idle line condition does not set the

RIDLE flag.

10.9.4.5 Overrun Flag (OR)—Bit 11

This bit is set when software fails to read the SCI Data Register (SCIDR) before the Receive

Shift register receives the next frame. The data in the Shift register is lost, but the data already in

the SCI Data register is not affected. Clear OR by reading the SCI Status Register (SCISR) with

OR set, then write the SCISR with any value.

•

0 = No overrun

•

1 = Overrun

10.9.4.6 Noise Flag (NF)—Bit 10

This bit is set when the SCI detects noise on the receiver input. The NF bit is set during the same

cycle as the RDRF flag, but it is not set in the case of an overrun. Clear NF by reading the SCISR

then write the SCI Status register with any value.

•

0 = No noise

•1 = Noise

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